1 // SPDX-License-Identifier: GPL-2.0-or-later
3  * MHI PCI driver - MHI over PCI controller driver
5  * This module is a generic driver for registering MHI-over-PCI devices,
6  * such as PCIe QCOM modems.
35  * struct mhi_pci_dev_info - MHI PCI device specific information
291 	.name = "qcom-qdu100",
372 	.name = "qcom-sa8775p",
382 	.name = "qcom-sdx75m",
393 	.name = "qcom-sdx65m",
404 	.name = "qcom-sdx55m",
416 	.name = "qcom-sdx24",
435 	/* The EDL firmware is a flash-programmer exposing firehose protocol */
459 	.name = "quectel-em1xx",
469 	.name = "quectel-rm5xx",
520 	.name = "foxconn-sdx55",
531 	.name = "foxconn-t99w175",
542 	.name = "foxconn-dw5930e",
553 	.name = "foxconn-t99w368",
564 	.name = "foxconn-t99w373",
575 	.name = "foxconn-t99w510",
586 	.name = "foxconn-dw5932e",
597 	.name = "foxconn-t99w515",
608 	.name = "foxconn-dw5934e",
646 	.name = "cinterion-mv31",
654 	.name = "cinterion-mv32",
694 	.name = "sierra-em919x",
726 	.name = "telit-fn980-hwv1",
768 	.name = "telit-fn990",
777 	.name = "telit-fe990a",
786 	.name = "netprisma-lcur57",
796 	.name = "netprisma-fcun69",
813 	/* EM919x (sdx55), use the same vid:pid as qcom-sdx55m */
831 	/* QDU100, x100-DU */
834 	{ PCI_DEVICE(PCI_VENDOR_ID_QUECTEL, 0x1001), /* EM120R-GL (sdx24) */
836 	{ PCI_DEVICE(PCI_VENDOR_ID_QUECTEL, 0x1002), /* EM160R-GL (sdx24) */
838 	/* RM520N-GL (sdx6x), eSIM */
841 	/* RM520N-GL (sdx6x), Lenovo variant */
844 	{ PCI_DEVICE(PCI_VENDOR_ID_QUECTEL, 0x100d), /* EM160R-GL (sdx24) */
846 	{ PCI_DEVICE(PCI_VENDOR_ID_QUECTEL, 0x2001), /* EM120R-GL for FCCL (sdx24) */
848 	/* T99W175 (sdx55), Both for eSIM and Non-eSIM */
854 	/* DW5930e (sdx55), Non-eSIM, It's also T99W175 */
878 	/* DW5932e-eSIM (sdx62), With eSIM */
881 	/* DW5932e (sdx62), Non-eSIM */
890 	/* DW5934e(sdx72), Non-eSIM */
893 	/* MV31-W (Cinterion) */
896 	/* MV31-W (Cinterion), based on new baseline */
899 	/* MV32-WA (Cinterion) */
902 	/* MV32-WB (Cinterion) */
947 	struct pci_dev *pdev = to_pci_dev(mhi_cntrl->cntrl_dev);  in mhi_pci_status_cb()
953 		dev_warn(&pdev->dev, "firmware crashed (%u)\n", cb);  in mhi_pci_status_cb()
954 		pm_runtime_forbid(&pdev->dev);  in mhi_pci_status_cb()
957 		pm_runtime_allow(&pdev->dev);  in mhi_pci_status_cb()
966 	/* no-op */  in mhi_pci_wake_get_nop()
971 	/* no-op */  in mhi_pci_wake_put_nop()
976 	/* no-op */  in mhi_pci_wake_toggle_nop()
981 	struct pci_dev *pdev = to_pci_dev(mhi_cntrl->cntrl_dev);  in mhi_pci_is_alive()
996 	struct pci_dev *pdev = to_pci_dev(mhi_cntrl->cntrl_dev);  in mhi_pci_claim()
1005 		dev_err(&pdev->dev, "failed to enable pci device: %d\n", err);  in mhi_pci_claim()
1009 	mhi_cntrl->regs = pcim_iomap_region(pdev, bar_num, pci_name(pdev));  in mhi_pci_claim()
1010 	if (IS_ERR(mhi_cntrl->regs)) {  in mhi_pci_claim()
1011 		err = PTR_ERR(mhi_cntrl->regs);  in mhi_pci_claim()
1012 		dev_err(&pdev->dev, "failed to map pci region: %d\n", err);  in mhi_pci_claim()
1015 	mhi_cntrl->reg_len = pci_resource_len(pdev, bar_num);  in mhi_pci_claim()
1017 	err = dma_set_mask_and_coherent(&pdev->dev, dma_mask);  in mhi_pci_claim()
1019 		dev_err(&pdev->dev, "Cannot set proper DMA mask\n");  in mhi_pci_claim()
1031 	struct pci_dev *pdev = to_pci_dev(mhi_cntrl->cntrl_dev);  in mhi_pci_get_irqs()
1039 	mhi_cntrl->nr_irqs = 1 + mhi_cntrl_config->num_events;  in mhi_pci_get_irqs()
1041 	nr_vectors = pci_alloc_irq_vectors(pdev, 1, mhi_cntrl->nr_irqs, PCI_IRQ_MSIX | PCI_IRQ_MSI);  in mhi_pci_get_irqs()
1043 		dev_err(&pdev->dev, "Error allocating MSI vectors %d\n",  in mhi_pci_get_irqs()
1048 	if (nr_vectors < mhi_cntrl->nr_irqs) {  in mhi_pci_get_irqs()
1049 		dev_warn(&pdev->dev, "using shared MSI\n");  in mhi_pci_get_irqs()
1052 		for (i = 0; i < mhi_cntrl_config->num_events; i++)  in mhi_pci_get_irqs()
1053 			mhi_cntrl_config->event_cfg[i].irq = 0;  in mhi_pci_get_irqs()
1054 		mhi_cntrl->nr_irqs = 1;  in mhi_pci_get_irqs()
1057 	irq = devm_kcalloc(&pdev->dev, mhi_cntrl->nr_irqs, sizeof(int), GFP_KERNEL);  in mhi_pci_get_irqs()
1059 		return -ENOMEM;  in mhi_pci_get_irqs()
1061 	for (i = 0; i < mhi_cntrl->nr_irqs; i++) {  in mhi_pci_get_irqs()
1062 		int vector = i >= nr_vectors ? (nr_vectors - 1) : i;  in mhi_pci_get_irqs()
1067 	mhi_cntrl->irq = irq;  in mhi_pci_get_irqs()
1077 	return pm_runtime_get(mhi_cntrl->cntrl_dev);  in mhi_pci_runtime_get()
1085 	pm_runtime_mark_last_busy(mhi_cntrl->cntrl_dev);  in mhi_pci_runtime_put()
1086 	pm_runtime_put(mhi_cntrl->cntrl_dev);  in mhi_pci_runtime_put()
1093 	struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl;  in mhi_pci_recovery_work()
1094 	struct pci_dev *pdev = to_pci_dev(mhi_cntrl->cntrl_dev);  in mhi_pci_recovery_work()
1097 	dev_warn(&pdev->dev, "device recovery started\n");  in mhi_pci_recovery_work()
1099 	timer_delete(&mhi_pdev->health_check_timer);  in mhi_pci_recovery_work()
1100 	pm_runtime_forbid(&pdev->dev);  in mhi_pci_recovery_work()
1103 	if (test_and_clear_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status)) {  in mhi_pci_recovery_work()
1109 	pci_load_saved_state(pdev, mhi_pdev->pci_state);  in mhi_pci_recovery_work()
1123 	dev_dbg(&pdev->dev, "Recovery completed\n");  in mhi_pci_recovery_work()
1125 	set_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status);  in mhi_pci_recovery_work()
1126 	mod_timer(&mhi_pdev->health_check_timer, jiffies + HEALTH_CHECK_PERIOD);  in mhi_pci_recovery_work()
1134 		dev_err(&pdev->dev, "Recovery failed: %d\n", err);  in mhi_pci_recovery_work()
1140 	struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl;  in health_check()
1142 	if (!test_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status) ||  in health_check()
1143 			test_bit(MHI_PCI_DEV_SUSPENDED, &mhi_pdev->status))  in health_check()
1147 		dev_err(mhi_cntrl->cntrl_dev, "Device died\n");  in health_check()
1148 		queue_work(system_long_wq, &mhi_pdev->recovery_work);  in health_check()
1153 	mod_timer(&mhi_pdev->health_check_timer, jiffies + HEALTH_CHECK_PERIOD);  in health_check()
1158 	void __iomem *base = mhi_cntrl->regs;  in mhi_pci_generic_edl_trigger()
1163 	ret = mhi_device_get_sync(mhi_cntrl->mhi_dev);  in mhi_pci_generic_edl_trigger()
1165 		dev_err(mhi_cntrl->cntrl_dev, "Failed to wakeup the device\n");  in mhi_pci_generic_edl_trigger()
1169 	pm_wakeup_event(&mhi_cntrl->mhi_dev->dev, 0);  in mhi_pci_generic_edl_trigger()
1170 	mhi_cntrl->runtime_get(mhi_cntrl);  in mhi_pci_generic_edl_trigger()
1178 	mhi_cntrl->write_reg(mhi_cntrl, edl_db + 4, upper_32_bits(MHI_EDL_COOKIE));  in mhi_pci_generic_edl_trigger()
1179 	mhi_cntrl->write_reg(mhi_cntrl, edl_db, lower_32_bits(MHI_EDL_COOKIE));  in mhi_pci_generic_edl_trigger()
1184 	mhi_cntrl->runtime_put(mhi_cntrl);  in mhi_pci_generic_edl_trigger()
1185 	mhi_device_put(mhi_cntrl->mhi_dev);  in mhi_pci_generic_edl_trigger()
1192 	const struct mhi_pci_dev_info *info = (struct mhi_pci_dev_info *) id->driver_data;  in mhi_pci_probe()
1198 	dev_info(&pdev->dev, "MHI PCI device found: %s\n", info->name);  in mhi_pci_probe()
1200 	/* mhi_pdev.mhi_cntrl must be zero-initialized */  in mhi_pci_probe()
1201 	mhi_pdev = devm_kzalloc(&pdev->dev, sizeof(*mhi_pdev), GFP_KERNEL);  in mhi_pci_probe()
1203 		return -ENOMEM;  in mhi_pci_probe()
1205 	INIT_WORK(&mhi_pdev->recovery_work, mhi_pci_recovery_work);  in mhi_pci_probe()
1206 	timer_setup(&mhi_pdev->health_check_timer, health_check, 0);  in mhi_pci_probe()
1208 	mhi_cntrl_config = info->config;  in mhi_pci_probe()
1209 	mhi_cntrl = &mhi_pdev->mhi_cntrl;  in mhi_pci_probe()
1211 	mhi_cntrl->cntrl_dev = &pdev->dev;  in mhi_pci_probe()
1212 	mhi_cntrl->iova_start = 0;  in mhi_pci_probe()
1213 	mhi_cntrl->iova_stop = (dma_addr_t)DMA_BIT_MASK(info->dma_data_width);  in mhi_pci_probe()
1214 	mhi_cntrl->fw_image = info->fw;  in mhi_pci_probe()
1215 	mhi_cntrl->edl_image = info->edl;  in mhi_pci_probe()
1217 	mhi_cntrl->read_reg = mhi_pci_read_reg;  in mhi_pci_probe()
1218 	mhi_cntrl->write_reg = mhi_pci_write_reg;  in mhi_pci_probe()
1219 	mhi_cntrl->status_cb = mhi_pci_status_cb;  in mhi_pci_probe()
1220 	mhi_cntrl->runtime_get = mhi_pci_runtime_get;  in mhi_pci_probe()
1221 	mhi_cntrl->runtime_put = mhi_pci_runtime_put;  in mhi_pci_probe()
1222 	mhi_cntrl->mru = info->mru_default;  in mhi_pci_probe()
1223 	mhi_cntrl->name = info->name;  in mhi_pci_probe()
1225 	if (info->edl_trigger)  in mhi_pci_probe()
1226 		mhi_cntrl->edl_trigger = mhi_pci_generic_edl_trigger;  in mhi_pci_probe()
1228 	if (info->sideband_wake) {  in mhi_pci_probe()
1229 		mhi_cntrl->wake_get = mhi_pci_wake_get_nop;  in mhi_pci_probe()
1230 		mhi_cntrl->wake_put = mhi_pci_wake_put_nop;  in mhi_pci_probe()
1231 		mhi_cntrl->wake_toggle = mhi_pci_wake_toggle_nop;  in mhi_pci_probe()
1234 	err = mhi_pci_claim(mhi_cntrl, info->bar_num, DMA_BIT_MASK(info->dma_data_width));  in mhi_pci_probe()
1248 	mhi_pdev->pci_state = pci_store_saved_state(pdev);  in mhi_pci_probe()
1258 		dev_err(&pdev->dev, "failed to prepare MHI controller\n");  in mhi_pci_probe()
1264 		dev_err(&pdev->dev, "failed to power up MHI controller\n");  in mhi_pci_probe()
1268 	set_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status);  in mhi_pci_probe()
1271 	mod_timer(&mhi_pdev->health_check_timer, jiffies + HEALTH_CHECK_PERIOD);  in mhi_pci_probe()
1273 	/* Only allow runtime-suspend if PME capable (for wakeup) */  in mhi_pci_probe()
1275 		pm_runtime_set_autosuspend_delay(&pdev->dev, 2000);  in mhi_pci_probe()
1276 		pm_runtime_use_autosuspend(&pdev->dev);  in mhi_pci_probe()
1277 		pm_runtime_mark_last_busy(&pdev->dev);  in mhi_pci_probe()
1278 		pm_runtime_put_noidle(&pdev->dev);  in mhi_pci_probe()
1294 	struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl;  in mhi_pci_remove()
1296 	timer_delete_sync(&mhi_pdev->health_check_timer);  in mhi_pci_remove()
1297 	cancel_work_sync(&mhi_pdev->recovery_work);  in mhi_pci_remove()
1299 	if (test_and_clear_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status)) {  in mhi_pci_remove()
1306 		pm_runtime_get_noresume(&pdev->dev);  in mhi_pci_remove()
1320 	struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl;  in mhi_pci_reset_prepare()
1322 	dev_info(&pdev->dev, "reset\n");  in mhi_pci_reset_prepare()
1324 	timer_delete(&mhi_pdev->health_check_timer);  in mhi_pci_reset_prepare()
1327 	if (test_and_clear_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status)) {  in mhi_pci_reset_prepare()
1342 	struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl;  in mhi_pci_reset_done()
1346 	pci_load_saved_state(pdev, mhi_pdev->pci_state);  in mhi_pci_reset_done()
1351 		dev_err(&pdev->dev, "reset failed\n");  in mhi_pci_reset_done()
1357 		dev_err(&pdev->dev, "failed to prepare MHI controller\n");  in mhi_pci_reset_done()
1363 		dev_err(&pdev->dev, "failed to power up MHI controller\n");  in mhi_pci_reset_done()
1368 	set_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status);  in mhi_pci_reset_done()
1369 	mod_timer(&mhi_pdev->health_check_timer, jiffies + HEALTH_CHECK_PERIOD);  in mhi_pci_reset_done()
1376 	struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl;  in mhi_pci_error_detected()
1378 	dev_err(&pdev->dev, "PCI error detected, state = %u\n", state);  in mhi_pci_error_detected()
1384 	if (test_and_clear_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status)) {  in mhi_pci_error_detected()
1400 		dev_err(&pdev->dev, "Cannot re-enable PCI device after reset.\n");  in mhi_pci_slot_reset()
1411 	dev_err(&pdev->dev, "PCI slot reset done\n");  in mhi_pci_io_resume()
1413 	queue_work(system_long_wq, &mhi_pdev->recovery_work);  in mhi_pci_io_resume()
1428 	struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl;  in mhi_pci_runtime_suspend()
1431 	if (test_and_set_bit(MHI_PCI_DEV_SUSPENDED, &mhi_pdev->status))  in mhi_pci_runtime_suspend()
1434 	timer_delete(&mhi_pdev->health_check_timer);  in mhi_pci_runtime_suspend()
1435 	cancel_work_sync(&mhi_pdev->recovery_work);  in mhi_pci_runtime_suspend()
1437 	if (!test_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status) ||  in mhi_pci_runtime_suspend()
1438 			mhi_cntrl->ee != MHI_EE_AMSS)  in mhi_pci_runtime_suspend()
1444 		dev_err(&pdev->dev, "failed to suspend device: %d\n", err);  in mhi_pci_runtime_suspend()
1445 		clear_bit(MHI_PCI_DEV_SUSPENDED, &mhi_pdev->status);  in mhi_pci_runtime_suspend()
1446 		return -EBUSY;  in mhi_pci_runtime_suspend()
1460 	struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl;  in mhi_pci_runtime_resume()
1463 	if (!test_and_clear_bit(MHI_PCI_DEV_SUSPENDED, &mhi_pdev->status))  in mhi_pci_runtime_resume()
1473 	if (!test_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status) ||  in mhi_pci_runtime_resume()
1474 			mhi_cntrl->ee != MHI_EE_AMSS)  in mhi_pci_runtime_resume()
1480 		dev_err(&pdev->dev, "failed to resume device: %d\n", err);  in mhi_pci_runtime_resume()
1485 	mod_timer(&mhi_pdev->health_check_timer, jiffies + HEALTH_CHECK_PERIOD);  in mhi_pci_runtime_resume()
1498 	queue_work(system_long_wq, &mhi_pdev->recovery_work);  in mhi_pci_runtime_resume()
1526 	struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl;  in mhi_pci_freeze()
1533 	flush_work(&mhi_pdev->recovery_work);  in mhi_pci_freeze()
1534 	if (test_and_clear_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status)) {  in mhi_pci_freeze()
1547 	queue_work(system_long_wq, &mhi_pdev->recovery_work);  in mhi_pci_restore()
1565 	.name		= "mhi-pci-generic",