Lines Matching +full:queue +full:- +full:rx
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
48 /* Registers for MSI-X */
96 * Host-Device interface is active
97 * Host-Device interface is inactive(as reflected by IPC_SLEEP_CONTROL_CSR_AD)
98 * Host-Device interface is inactive(as reflected by IPC_SLEEP_CONTROL_CSR_AD)
126 /* Minimum and Maximum number of MSI-X Vector
138 /* The number of descriptors in TX/RX queues */
141 /* Number of Queue for TX and RX
150 /* The size of DMA buffer for TX and RX in bytes */
161 /* Number of pending RX requests for downlink */
173 * All members are write-only for host and read-only for device.
186 * @addr_tfdq: Address of TFD Queue(tx)
187 * @addr_urbdq0: Address of URBD Queue(tx)
188 * @num_tfdq: Number of TFD in TFD Queue(tx)
189 * @num_urbdq0: Number of URBD in URBD Queue(tx)
190 * @tfdq_db_vec: Queue number of TFD
191 * @urbdq0_db_vec: Queue number of URBD
192 * @addr_frbdq: Address of FRBD Queue(rx)
193 * @addr_urbdq1: Address of URBD Queue(rx)
194 * @num_frbdq: Number of FRBD in FRBD Queue(rx)
195 * @frbdq_db_vec: Queue number of FRBD
196 * @num_urbdq1: Number of URBD in URBD Queue(rx)
197 * @urbdq_db_vec: Queue number of URBDQ1
198 * @tr_msi_vec: Transfer Ring MSI-X Vector
199 * @cr_msi_vec: Completion Ring MSI-X Vector
272 * @num_txq: Queue index of TFD Queue
284 /* FRB Descriptor for RX
285 * @tag: RX buffer tag (index of RX buffer queue)
295 /* URB Descriptor for RX
306 /* RFH header in RX packet
308 * @rxq: RX Queue number
340 /* Structure for TX Queue
360 /* Structure for RX Queue
415 * @irq_lock: spinlock for MSI-X
416 * @hci_rx_lock: spinlock for HCI RX flow
418 * @msix_entries: array of MSI-X entries
419 * @msix_enabled: true if MSI-X is enabled;
432 * @workqueue: workqueue for RX work
433 * @rx_skb_q: SKB queue for RX packet
434 * @rx_work: RX work struct to process the RX packet in @rx_skb_q
441 * @txq: TX Queue struct
442 * @rxq: RX Queue struct
450 /* lock used in MSI-X interrupt */
452 /* lock to serialize rx events */
498 return ioread32(data->base_addr + offset); in btintel_pcie_rd_reg32()
504 iowrite8(val, data->base_addr + offset); in btintel_pcie_wr_reg8()
510 iowrite32(val, data->base_addr + offset); in btintel_pcie_wr_reg32()
518 r = ioread32(data->base_addr + offset); in btintel_pcie_set_reg_bits()
520 iowrite32(r, data->base_addr + offset); in btintel_pcie_set_reg_bits()
528 r = ioread32(data->base_addr + offset); in btintel_pcie_clr_reg_bits()
530 iowrite32(r, data->base_addr + offset); in btintel_pcie_clr_reg_bits()