1 /* SPDX-License-Identifier: GPL-2.0-or-later */
48 /* Registers for MSI-X */
96  * Host-Device interface is active
97  * Host-Device interface is inactive(as reflected by IPC_SLEEP_CONTROL_CSR_AD)
98  * Host-Device interface is inactive(as reflected by IPC_SLEEP_CONTROL_CSR_AD)
126 /* Minimum and Maximum number of MSI-X Vector
173  * All members are write-only for host and read-only for device.
198  * @tr_msi_vec: Transfer Ring MSI-X Vector
199  * @cr_msi_vec: Completion Ring MSI-X Vector
415  * @irq_lock: spinlock for MSI-X
418  * @msix_entries: array of MSI-X entries
419  * @msix_enabled: true if MSI-X is enabled;
450 	/* lock used in MSI-X interrupt */
496 					u32 offset)  in btintel_pcie_rd_reg32()  argument
498 	return ioread32(data->base_addr + offset);  in btintel_pcie_rd_reg32()
502 					u32 offset, u8 val)  in btintel_pcie_wr_reg8()  argument
504 	iowrite8(val, data->base_addr + offset);  in btintel_pcie_wr_reg8()
508 					 u32 offset, u32 val)  in btintel_pcie_wr_reg32()  argument
510 	iowrite32(val, data->base_addr + offset);  in btintel_pcie_wr_reg32()
514 					     u32 offset, u32 bits)  in btintel_pcie_set_reg_bits()  argument
518 	r = ioread32(data->base_addr + offset);  in btintel_pcie_set_reg_bits()
520 	iowrite32(r, data->base_addr + offset);  in btintel_pcie_set_reg_bits()
524 					     u32 offset, u32 bits)  in btintel_pcie_clr_reg_bits()  argument
528 	r = ioread32(data->base_addr + offset);  in btintel_pcie_clr_reg_bits()
530 	iowrite32(r, data->base_addr + offset);  in btintel_pcie_clr_reg_bits()