Lines Matching +full:os +full:- +full:initiated
1 /* SPDX-License-Identifier: MIT */
3 * Copyright (c) 2020-2024, Intel Corporation.
11 * fw_bin_header->api_version[VPU_BOOT_API_VER_ID] = (VPU_BOOT_API_VER_MAJOR << 16) |
68 * Size of primary preemption buffer, assuming a 2-job submission queue.
74 * Size of secondary preemption buffer, assuming a 2-job submission queue.
86 /* Space reserved for future preemption-related fields. */
109 /** VPU scheduling mode. By default, OS scheduling is used. */
221 /* Clock frequencies: 0x20 - 0xFF */
226 /* Memory regions: 0x100 - 0x1FF */
246 /* IRQ re-direct numbers: 0x200 - 0x2FF */
249 /* ARM -> VPU doorbell interrupt. ARM is notifying VPU of async command or compute job. */
251 /* VPU -> ARM job done interrupt. VPU is notifying ARM of compute job completion. */
253 /* VPU -> ARM IRQ line to use to request MMU update. */
255 /* ARM -> VPU IRQ line to use to notify of MMU update completion. */
257 /* ARM -> VPU IRQ line to use to request power level change. */
259 /* VPU -> ARM IRQ line to use to notify of power level change completion. */
261 /* VPU -> ARM IRQ line to use to notify of VPU idle state change */
263 /* VPU -> ARM IRQ line to use to request counter reset. */
265 /* ARM -> VPU IRQ line to use to notify of counter reset completion. */
267 /* VPU -> ARM IRQ line to use to notify of preemption completion. */
271 /* Silicon information: 0x300 - 0x3FF */
286 * TODO: EISW-33556: Move log level definition (mvLog_t) to this file.
320 * 0 - Default, DVFS mode selected by the firmware
321 * 1 - Max Performance
322 * 2 - On Demand
323 * 3 - Power Save
324 * 4 - On Demand Priority Aware
329 * On-demand: Default if 0.
330 * Bit 0-7 - uint8_t: Highest residency percent
331 * Bit 8-15 - uint8_t: High residency percent
332 * Bit 16-23 - uint8_t: Low residency percent
333 * Bit 24-31 - uint8_t: Lowest residency percent
334 * Bit 32-35 - unsigned 4b: PLL Ratio increase amount on highest residency
335 * Bit 36-39 - unsigned 4b: PLL Ratio increase amount on high residency
336 * Bit 40-43 - unsigned 4b: PLL Ratio decrease amount on low residency
337 * Bit 44-47 - unsigned 4b: PLL Ratio decrease amount on lowest frequency
338 * Bit 48-55 - uint8_t: Period (ms) for residency decisions
339 * Bit 56-63 - uint8_t: Averaging windows (as multiples of period. Max: 30 decimal)
370 /* Warm boot information: 0x400 - 0x43F */
375 /* Power States transitions timestamps: 0x440 - 0x46F*/
377 /* VPU_IDLE -> VPU_ACTIVE transition initiated timestamp */
379 /* VPU_IDLE -> VPU_ACTIVE transition completed timestamp */
381 /* VPU_ACTIVE -> VPU_IDLE transition initiated timestamp */
383 /* VPU_ACTIVE -> VPU_IDLE transition completed timestamp */
385 /* VPU_IDLE -> VPU_STANDBY transition initiated timestamp */
387 /* VPU_IDLE -> VPU_STANDBY transition completed timestamp */
402 /* Unused/reserved: 0x488 - 0xFFF */
440 /* legacy field - do not use */
454 * 0 - null terminated string
455 * 1 - size + null terminated string
456 * 2 - MIPI-SysT encoding
461 * 0 - messages are place 1 after another
462 * n - every message starts and multiple on offset