Lines Matching +full:0 +full:x600

37 #define DUART16552_PADDR	(XCHAL_KIO_PADDR + 0x0D050020)
40 #define XTFPGA_FPGAREGS_VADDR	IOADDR(0x0D020000)
42 #define XTFPGA_CLKFRQ_VADDR	(XTFPGA_FPGAREGS_VADDR + 0x04)
44 #define DIP_SWITCHES_VADDR	(XTFPGA_FPGAREGS_VADDR + 0x0C)
45 /* Software reset (write 0xdead):  */
46 #define XTFPGA_SWRST_VADDR	(XTFPGA_FPGAREGS_VADDR + 0x10)
50 #define OETH_REGS_PADDR		(XCHAL_KIO_PADDR + 0x0D030000)
51 #define OETH_REGS_SIZE		0x1000
52 #define OETH_SRAMBUFF_PADDR	(XCHAL_KIO_PADDR + 0x0D800000)
55 #define OETH_SRAMBUFF_SIZE	(5 * 0x600 + 5 * 0x600)
57 #define C67X00_PADDR		(XCHAL_KIO_PADDR + 0x0D0D0000)
58 #define C67X00_SIZE		0x10