1 // SPDX-License-Identifier: GPL-2.0-only
48 		return reg - HV_X64_MSR_SINT0 + HV_X64_MSR_NESTED_SINT0;  in hv_get_nested_msr()
150  * Routines to do per-architecture handling of stimer0
239  * Hyper-V clock counter resets during hibernation. Save and restore clock
256 	 *                - reference counter (time) now.  in restore_hv_clock_tsc_state()
258 	hv_adj_sched_clock_offset(hv_ref_counter_at_suspend - hv_read_reference_counter());  in restore_hv_clock_tsc_state()
263  * functions of x86_platform. The Hyper-V clock counter is reset during
264  * suspend-resume and the offset used to measure time needs to be
323  * Prior to WS2016 Debug-VM sends NMIs to all CPUs which makes
329 	static atomic_t nmi_cpu = ATOMIC_INIT(-1);  in hv_nmi_unknown()
335 	old_cpu = -1;  in hv_nmi_unknown()
350 	return freq / 1000;  in hv_get_tsc_khz()
372 	 *  Override wakeup_secondary_cpu_64 callback for SEV-SNP  in hv_smp_prepare_cpus()
376 		apic->wakeup_secondary_cpu_64 = hv_snp_boot_ap;  in hv_smp_prepare_cpus()
399  * When a fully enlightened TDX VM runs on Hyper-V, the firmware sets the
401  * interrupts can't work because request_irq() -> ... -> irq_to_desc() returns
404  * later setup_IO_APIC_irqs() -> find_irq_entry() fails to find the legacy irqs
409  * 'default_legacy_pic'. This way, mp_config_acpi_legacy_irqs() sees a non-zero
424 		pr_err("%s: Could not detect Hyper-V version\n", __func__);  in hv_get_hypervisor_version()
425 		return -ENODEV;  in hv_get_hypervisor_version()
428 	cpuid(HYPERV_CPUID_VERSION, &info->eax, &info->ebx, &info->ecx, &info->edx);  in hv_get_hypervisor_version()
439 	pv_info.name = "Hyper-V";  in ms_hyperv_init_platform()
453 	pr_info("Hyper-V: privilege flags low %#x, high %#x, ext %#x, hints %#x, misc %#x\n",  in ms_hyperv_init_platform()
461 	pr_debug("Hyper-V: max %u virtual processors, %u logical processors\n",  in ms_hyperv_init_platform()
468 		pr_info("Hyper-V: running on a nested hypervisor\n");  in ms_hyperv_init_platform()
488 		pr_info("Hyper-V: Isolation Config: Group A 0x%x, Group B 0x%x\n",  in ms_hyperv_init_platform()
502 				 * Mark the Hyper-V TSC page feature as disabled  in ms_hyperv_init_platform()
512 				 * print a warning message. The slower Hyper-V MSR-based  in ms_hyperv_init_platform()
516 					pr_warn("Hyper-V: Invariant TSC is unavailable\n");  in ms_hyperv_init_platform()
521 				/* Don't trust Hyper-V's TLB-flushing hypercalls. */  in ms_hyperv_init_platform()
532 		pr_info("Hyper-V: Nested features: 0x%x\n",  in ms_hyperv_init_platform()
547 		pr_info("Hyper-V: LAPIC Timer Frequency: %#x\n",  in ms_hyperv_init_platform()
619 	 * Hyper-V doesn't provide irq remapping for IO-APIC. To enable x2apic,  in ms_hyperv_init_platform()
621 	 * and Hyper-V IOMMU driver makes sure cpus assigned with IO-APIC irqs  in ms_hyperv_init_platform()
622 	 * have 8-bit APIC id.  in ms_hyperv_init_platform()
629 	/* Register Hyper-V specific clocksource */  in ms_hyperv_init_platform()
635 	 * TSC should be marked as unstable only after Hyper-V  in ms_hyperv_init_platform()
640 		mark_tsc_unstable("running on Hyper-V");  in ms_hyperv_init_platform()
652  * returns -ENODEV and the Hyper-V IOMMU driver is not used; instead, the
653  * generic support of the 15-bit APIC ID is used: see __irq_msi_compose_msg().
655  * Note: for a VM on Hyper-V, the I/O-APIC is the only device which
657  * There is no HPET, and PCI MSI/MSI-X interrupts are remapped by the
658  * pci-hyperv host bridge.
660  * Note: for a Hyper-V root partition, this will always return false.
662  * default, they are implemented as intercepts by the Windows Hyper-V stack.
682 	ghcb_set_rcx(ghcb, regs->cx);  in hv_sev_es_hcall_prepare()
683 	ghcb_set_rdx(ghcb, regs->dx);  in hv_sev_es_hcall_prepare()
684 	ghcb_set_r8(ghcb, regs->r8);  in hv_sev_es_hcall_prepare()
695 	.name			= "Microsoft Hyper-V",