1 // SPDX-License-Identifier: GPL-2.0-only
15  * Copyright (c) 2010-17:  Borislav Petkov <bp@alien8.de>
48 	SW_INJ = 0,	/* SW injection, simply decode the error */
56 	[SW_INJ] = "sw",
71 	m->reg = val;							\
85 	*val = m->reg;							\
100 /* Use the user provided IPID value on a sw injection. */
107 			m->ipid = val;  in inj_ipid_set()
119 	m->cpuvendor = boot_cpu_data.x86_vendor;  in setup_inj_struct()
120 	m->time	     = ktime_get_real_seconds();  in setup_inj_struct()
121 	m->cpuid     = cpuid_eax(1);  in setup_inj_struct()
122 	m->microcode = boot_cpu_data.microcode;  in setup_inj_struct()
128 	struct mce *i = &per_cpu(injectm, m->extcpu);  in inject_mce()
131 	i->finished = 0;  in inject_mce()
133 	m->finished = 0;  in inject_mce()
135 	i->extcpu = m->extcpu;  in inject_mce()
141 	i->finished = 1;  in inject_mce()
153 	m->finished = 0;  in raise_poll()
163 		regs.ip = m->ip;  in raise_exception()
164 		regs.cs = m->cs;  in raise_exception()
167 	/* do_machine_check() expects interrupts disabled -- at least */  in raise_exception()
171 	m->finished = 0;  in raise_exception()
184 	if (m->inject_flags & MCJ_EXCEPTION)  in mce_raise_notify()
186 	else if (m->status)  in mce_raise_notify()
197 			m->inject_flags & MCJ_EXCEPTION) {  in mce_irq_ipi()
207 	int context = MCJ_CTX(m->inject_flags);  in raise_local()
209 	int cpu = m->extcpu;  in raise_local()
211 	if (m->inject_flags & MCJ_EXCEPTION) {  in raise_local()
212 		pr_info("Triggering MCE exception on CPU %d\n", cpu);  in raise_local()
226 			ret = -EINVAL;  in raise_local()
228 		pr_info("MCE exception done on CPU %d\n", cpu);  in raise_local()
229 	} else if (m->status) {  in raise_local()
234 		m->finished = 0;  in raise_local()
241 	int context = MCJ_CTX(m->inject_flags);  in raise_mce()
248 	if (m->inject_flags & (MCJ_IRQ_BROADCAST | MCJ_NMI_BROADCAST)) {  in raise_mce()
257 			if (!mcpu->finished ||  in raise_mce()
258 			    MCJ_CTX(mcpu->inject_flags) != MCJ_CTX_RANDOM)  in raise_mce()
262 			if (m->inject_flags & MCJ_IRQ_BROADCAST) {  in raise_mce()
271 			} else if (m->inject_flags & MCJ_NMI_BROADCAST)  in raise_mce()
348 	return -EINVAL;  in __set_inj()
369 		return -EINVAL;  in flags_write()
372 		return -EFAULT;  in flags_write()
374 	buf[cnt - 1] = 0;  in flags_write()
407 		return -EINVAL;  in inj_extcpu_set()
409 	m->extcpu = val;  in inj_extcpu_set()
449 	F3 = nb->misc;  in toggle_nb_mca_mst_cpu()
456 		       __func__, PCI_FUNC(F3->devfn), NBCFG);  in toggle_nb_mca_mst_cpu()
470 		       __func__, PCI_FUNC(F3->devfn), NBCFG);  in toggle_nb_mca_mst_cpu()
533 	 * - MCx_STATUS[Deferred]: make sure it is a deferred error  in do_inject()
534 	 * - MCx_STATUS[UC] cleared: deferred errors are _not_ UC  in do_inject()
591 	/* Get bank count on target CPU so we can handle non-uniform values. */  in inj_bank_set()
592 	rdmsrl_on_cpu(m->extcpu, MSR_IA32_MCG_CAP, &cap);  in inj_bank_set()
596 		pr_err("MCA bank %llu non-existent on CPU%d\n", val, m->extcpu);  in inj_bank_set()
597 		return -EINVAL;  in inj_bank_set()
600 	m->bank = val;  in inj_bank_set()
603 	 * sw-only injection allows to write arbitrary values into the MCA  in inj_bank_set()
616 		if (rdmsrl_on_cpu(m->extcpu, MSR_AMD64_SMCA_MCx_IPID(val), &ipid)) {  in inj_bank_set()
617 			pr_err("Error reading IPID on CPU%d\n", m->extcpu);  in inj_bank_set()
618 			return -EINVAL;  in inj_bank_set()
623 			return -ENODEV;  in inj_bank_set()
663 "\t banks in a processor varies and is family/model-specific, therefore, the\n"
664 "\t supplied value is sanity-checked. Setting the bank value also triggers the\n"
672 "\t  - \"sw\": Software error injection. Decode error to a human-readable \n"
674 "\t  - \"hw\": Hardware error injection. Causes the #MC exception handler to \n"
678 "\t  - \"df\": Trigger APIC interrupt for Deferred error. Causes deferred \n"
681 "\t  - \"th\": Trigger APIC interrupt for Threshold errors. Causes threshold \n"
684 "ipid:\t IPID (AMD-specific)\n"
719 	dfs_inj = debugfs_create_dir("mce-inject", NULL);  in debugfs_init()
771 		return -ENOMEM;  in inject_init()