Lines Matching +full:broken +full:- +full:turn +full:- +full:around
1 // SPDX-License-Identifier: GPL-2.0
19 #include <asm/intel-family.h>
30 * Processors which have self-snooping capability can handle conflicting
38 switch (c->x86_vfm) { in check_memory_type_self_snoop_errata()
70 if (c->x86 != 6) in probe_xeon_phi_r3mwait()
72 switch (c->x86_vfm) { in probe_xeon_phi_r3mwait()
92 * Early microcode releases for the Spectre v2 mitigation were broken.
94 * - https://newsroom.intel.com/wp-content/uploads/sites/11/2018/03/microcode-update-guidance.pdf
95 * - https://kb.vmware.com/s/article/52345
96 * - Microcode revisions observed in the wild
97 * - Release note from 20180108 microcode release
140 if (c->x86_vfm == spectre_bad_microcodes[i].vfm && in bad_spectre_microcode()
141 c->x86_stepping == spectre_bad_microcodes[i].stepping) in bad_spectre_microcode()
142 return (c->microcode <= spectre_bad_microcodes[i].microcode); in bad_spectre_microcode()
179 c->x86_phys_bits -= keyid_bits; in detect_tme_early()
189 if (c->x86_vfm < INTEL_PENTIUM_M_DOTHAN) in intel_unlock_cpuid_leafs()
197 c->cpuid_level = cpuid_eax(0); in intel_unlock_cpuid_leafs()
204 if (c->x86 >= 6 && !cpu_has(c, X86_FEATURE_IA64)) in early_init_intel()
205 c->microcode = intel_get_microcode_revision(); in early_init_intel()
212 pr_warn("Intel Spectre v2 broken microcode detected; disabling Speculation Control\n"); in early_init_intel()
227 * a large page. This is worked around in microcode, but we in early_init_intel()
231 if (c->x86_vfm == INTEL_ATOM_BONNELL && c->x86_stepping <= 2 && in early_init_intel()
232 c->microcode < 0x20e) { in early_init_intel()
241 if (c->x86 == 15 && c->x86_cache_alignment == 64) in early_init_intel()
242 c->x86_cache_alignment = 128; in early_init_intel()
246 if (c->x86_vfm == INTEL_P4_PRESCOTT && in early_init_intel()
247 (c->x86_stepping == 0x3 || c->x86_stepping == 0x4)) in early_init_intel()
248 c->x86_phys_bits = 36; in early_init_intel()
251 * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate in early_init_intel()
252 * with P/T states and does not stop in deep C-states. in early_init_intel()
255 * cabinets - we turn it off in that case explicitly.) in early_init_intel()
257 * Use a model-specific check for some older CPUs that have invariant in early_init_intel()
260 if (c->x86_power & (1 << 8)) { in early_init_intel()
263 } else if ((c->x86_vfm >= INTEL_P4_PRESCOTT && c->x86_vfm <= INTEL_P4_WILLAMETTE) || in early_init_intel()
264 (c->x86_vfm >= INTEL_CORE_YONAH && c->x86_vfm <= INTEL_IVYBRIDGE)) { in early_init_intel()
269 switch (c->x86_vfm) { in early_init_intel()
279 * PAT is broken on early family 6 CPUs, the last of which in early_init_intel()
289 if (c->x86_vfm >= INTEL_PENTIUM_PRO && in early_init_intel()
290 c->x86_vfm <= INTEL_CORE_YONAH) in early_init_intel()
298 * Adhere to the preference and program the Linux-defined fast in early_init_intel()
301 if (c->x86_vfm >= INTEL_PENTIUM_M_DOTHAN) { in early_init_intel()
323 if (c->x86_vfm == INTEL_QUARK_X1000) { in early_init_intel()
364 if (!c->cpu_index) in intel_smp_check()
370 if (c->x86_vfm >= INTEL_FAM5_START && c->x86_vfm < INTEL_PENTIUM_MMX && in intel_smp_check()
371 c->x86_stepping >= 1 && c->x86_stepping <= 4) { in intel_smp_check()
398 if (c->x86_vfm >= INTEL_FAM5_START && c->x86_vfm < INTEL_QUARK_X1000) { in intel_workarounds()
403 pr_notice("Intel Pentium with F0 0F bug - workaround enabled.\n"); in intel_workarounds()
413 if ((c->x86_vfm == INTEL_PENTIUM_II_KLAMATH && c->x86_stepping < 3) || in intel_workarounds()
414 c->x86_vfm < INTEL_PENTIUM_II_KLAMATH) in intel_workarounds()
432 if (c->x86_vfm == INTEL_P4_WILLAMETTE && c->x86_stepping == 1) { in intel_workarounds()
446 if (boot_cpu_has(X86_FEATURE_APIC) && c->x86_vfm == INTEL_PENTIUM_75 && in intel_workarounds()
447 (c->x86_stepping < 0x6 || c->x86_stepping == 0xb)) in intel_workarounds()
453 * both 8-byte aligned. PII/PIII only like MOVSL with 8-byte alignment. in intel_workarounds()
458 if (c->x86_vfm >= INTEL_PENTIUM_PRO) in intel_workarounds()
517 * ZMM registers (512-bit vectors) are used. On these CPUs, when the kernel
518 * executes SIMD-optimized code such as cryptography functions or CRCs, it
519 * should prefer 256-bit (YMM) code to 512-bit (ZMM) code.
542 if (c->cpuid_level > 9) { in init_intel()
563 (c->x86_vfm == INTEL_CORE2_DUNNINGTON || in init_intel()
564 c->x86_vfm == INTEL_NEHALEM_EX || in init_intel()
565 c->x86_vfm == INTEL_WESTMERE_EX)) in init_intel()
569 (c->x86_vfm == INTEL_ATOM_GOLDMONT || in init_intel()
570 c->x86_vfm == INTEL_LUNARLAKE_M)) in init_intel()
574 if (c->x86 == 15) in init_intel()
575 c->x86_cache_alignment = c->x86_clflush_size * 2; in init_intel()
582 if (c->x86 == 6) { in init_intel()
583 unsigned int l2 = c->x86_cache_size; in init_intel()
586 switch (c->x86_model) { in init_intel()
597 else if (c->x86_stepping == 0 || c->x86_stepping == 5) in init_intel()
598 p = "Celeron-A"; in init_intel()
608 strcpy(c->x86_model_id, p); in init_intel()
615 /* Work around errata */ in init_intel()
636 if (c->x86_vfm == INTEL_PENTIUM_III_TUALATIN && size == 0) in intel_size_cache()
640 * Intel Quark SoC X1000 contains a 4-way set associative in intel_size_cache()
643 if (c->x86_vfm == INTEL_QUARK_X1000) in intel_size_cache()
672 * All of leaf 0x2's one-byte TLB descriptors implies the same number of
688 { 0x01, TLB_INST_4K, 32}, /* TLB_INST 4 KByte pages, 4-way set associative */
690 { 0x03, TLB_DATA_4K, 64}, /* TLB_DATA 4 KByte pages, 4-way set associative */
691 { 0x04, TLB_DATA_4M, 8}, /* TLB_DATA 4 MByte pages, 4-way set associative */
692 { 0x05, TLB_DATA_4M, 32}, /* TLB_DATA 4 MByte pages, 4-way set associative */
693 { 0x0b, TLB_INST_4M, 4}, /* TLB_INST 4 MByte pages, 4-way set associative */
695 { 0x50, TLB_INST_ALL, 64}, /* TLB_INST 4 KByte and 2-MByte or 4-MByte pages */
696 { 0x51, TLB_INST_ALL, 128}, /* TLB_INST 4 KByte and 2-MByte or 4-MByte pages */
697 { 0x52, TLB_INST_ALL, 256}, /* TLB_INST 4 KByte and 2-MByte or 4-MByte pages */
698 { 0x55, TLB_INST_2M_4M, 7}, /* TLB_INST 2-MByte or 4-MByte pages, fully associative */
699 { 0x56, TLB_DATA0_4M, 16}, /* TLB_DATA0 4 MByte pages, 4-way set associative */
700 { 0x57, TLB_DATA0_4K, 16}, /* TLB_DATA0 4 KByte pages, 4-way associative */
702 { 0x5a, TLB_DATA0_2M_4M, 32}, /* TLB_DATA0 2-MByte or 4 MByte pages, 4-way set associative */
707 { 0x63, TLB_DATA_1G_2M_4M, 4}, /* TLB_DATA 1 GByte pages, 4-way set associative
709 { 0x6b, TLB_DATA_4K, 256}, /* TLB_DATA 4 KByte pages, 8-way associative */
710 { 0x6c, TLB_DATA_2M_4M, 128}, /* TLB_DATA 2 MByte or 4 MByte pages, 8-way associative */
712 { 0x76, TLB_INST_2M_4M, 8}, /* TLB_INST 2-MByte or 4-MByte pages, fully associative */
713 { 0xb0, TLB_INST_4K, 128}, /* TLB_INST 4 KByte pages, 4-way set associative */
714 { 0xb1, TLB_INST_2M_4M, 4}, /* TLB_INST 2M pages, 4-way, 8 entries or 4M pages, 4-way entries */
715 { 0xb2, TLB_INST_4K, 64}, /* TLB_INST 4KByte pages, 4-way set associative */
716 { 0xb3, TLB_DATA_4K, 128}, /* TLB_DATA 4 KByte pages, 4-way set associative */
717 { 0xb4, TLB_DATA_4K, 256}, /* TLB_DATA 4 KByte pages, 4-way associative */
718 { 0xb5, TLB_INST_4K, 64}, /* TLB_INST 4 KByte pages, 8-way set associative */
719 { 0xb6, TLB_INST_4K, 128}, /* TLB_INST 4 KByte pages, 8-way set associative */
720 { 0xba, TLB_DATA_4K, 64}, /* TLB_DATA 4 KByte pages, 4-way associative */
721 { 0xc0, TLB_DATA_4K_4M, 8}, /* TLB_DATA 4 KByte and 4 MByte pages, 4-way associative */
722 { 0xc1, STLB_4K_2M, 1024}, /* STLB 4 KByte and 2 MByte pages, 8-way associative */
723 { 0xc2, TLB_DATA_2M_4M, 16}, /* TLB_DATA 2 MByte/4MByte pages, 4-way associative */
724 { 0xca, STLB_4K, 512}, /* STLB 4 KByte pages, 4-way associative */
806 if (c->cpuid_level < 2) in intel_detect_tlb()
833 [0] = "486 DX-25/33",
834 [1] = "486 DX-50",
839 [7] = "486 DX/2-WB",
841 [9] = "486 DX/4-WB"
846 [0] = "Pentium 60/66 A-step",
848 [2] = "Pentium 75 - 200",
851 [7] = "Mobile Pentium 75 - 200",
858 [0] = "Pentium Pro A-step",