Lines Matching +full:4 +full:c
36 static void check_memory_type_self_snoop_errata(struct cpuinfo_x86 *c) in check_memory_type_self_snoop_errata() argument
38 switch (c->x86_vfm) { in check_memory_type_self_snoop_errata()
64 static void probe_xeon_phi_r3mwait(struct cpuinfo_x86 *c) in probe_xeon_phi_r3mwait() argument
70 if (c->x86 != 6) in probe_xeon_phi_r3mwait()
72 switch (c->x86_vfm) { in probe_xeon_phi_r3mwait()
83 set_cpu_cap(c, X86_FEATURE_RING3MWAIT); in probe_xeon_phi_r3mwait()
87 if (c == &boot_cpu_data) in probe_xeon_phi_r3mwait()
128 static bool bad_spectre_microcode(struct cpuinfo_x86 *c) in bad_spectre_microcode() argument
136 if (cpu_has(c, X86_FEATURE_HYPERVISOR)) in bad_spectre_microcode()
140 if (c->x86_vfm == spectre_bad_microcodes[i].vfm && in bad_spectre_microcode()
141 c->x86_stepping == spectre_bad_microcodes[i].stepping) in bad_spectre_microcode()
142 return (c->microcode <= spectre_bad_microcodes[i].microcode); in bad_spectre_microcode()
155 static void detect_tme_early(struct cpuinfo_x86 *c) in detect_tme_early() argument
164 clear_cpu_cap(c, X86_FEATURE_TME); in detect_tme_early()
179 c->x86_phys_bits -= keyid_bits; in detect_tme_early()
184 void intel_unlock_cpuid_leafs(struct cpuinfo_x86 *c) in intel_unlock_cpuid_leafs() argument
189 if (c->x86_vfm < INTEL_PENTIUM_M_DOTHAN) in intel_unlock_cpuid_leafs()
197 c->cpuid_level = cpuid_eax(0); in intel_unlock_cpuid_leafs()
200 static void early_init_intel(struct cpuinfo_x86 *c) in early_init_intel() argument
204 if (c->x86 >= 6 && !cpu_has(c, X86_FEATURE_IA64)) in early_init_intel()
205 c->microcode = intel_get_microcode_revision(); in early_init_intel()
208 if ((cpu_has(c, X86_FEATURE_SPEC_CTRL) || in early_init_intel()
209 cpu_has(c, X86_FEATURE_INTEL_STIBP) || in early_init_intel()
210 cpu_has(c, X86_FEATURE_IBRS) || cpu_has(c, X86_FEATURE_IBPB) || in early_init_intel()
211 cpu_has(c, X86_FEATURE_STIBP)) && bad_spectre_microcode(c)) { in early_init_intel()
231 if (c->x86_vfm == INTEL_ATOM_BONNELL && c->x86_stepping <= 2 && in early_init_intel()
232 c->microcode < 0x20e) { in early_init_intel()
234 clear_cpu_cap(c, X86_FEATURE_PSE); in early_init_intel()
238 set_cpu_cap(c, X86_FEATURE_SYSENTER32); in early_init_intel()
241 if (c->x86 == 15 && c->x86_cache_alignment == 64) in early_init_intel()
242 c->x86_cache_alignment = 128; in early_init_intel()
246 if (c->x86_vfm == INTEL_P4_PRESCOTT && in early_init_intel()
247 (c->x86_stepping == 0x3 || c->x86_stepping == 0x4)) in early_init_intel()
248 c->x86_phys_bits = 36; in early_init_intel()
251 * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate in early_init_intel()
252 * with P/T states and does not stop in deep C-states. in early_init_intel()
260 if (c->x86_power & (1 << 8)) { in early_init_intel()
261 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC); in early_init_intel()
262 set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC); in early_init_intel()
263 } else if ((c->x86_vfm >= INTEL_P4_PRESCOTT && c->x86_vfm <= INTEL_P4_WILLAMETTE) || in early_init_intel()
264 (c->x86_vfm >= INTEL_CORE_YONAH && c->x86_vfm <= INTEL_IVYBRIDGE)) { in early_init_intel()
265 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC); in early_init_intel()
269 switch (c->x86_vfm) { in early_init_intel()
274 set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC_S3); in early_init_intel()
289 if (c->x86_vfm >= INTEL_PENTIUM_PRO && in early_init_intel()
290 c->x86_vfm <= INTEL_CORE_YONAH) in early_init_intel()
291 clear_cpu_cap(c, X86_FEATURE_PAT); in early_init_intel()
301 if (c->x86_vfm >= INTEL_PENTIUM_M_DOTHAN) { in early_init_intel()
305 set_cpu_cap(c, X86_FEATURE_REP_GOOD); in early_init_intel()
323 if (c->x86_vfm == INTEL_QUARK_X1000) { in early_init_intel()
328 check_memory_type_self_snoop_errata(c); in early_init_intel()
334 if (cpu_has(c, X86_FEATURE_TME)) in early_init_intel()
335 detect_tme_early(c); in early_init_intel()
338 static void bsp_init_intel(struct cpuinfo_x86 *c) in bsp_init_intel() argument
340 resctrl_cpu_detect(c); in bsp_init_intel()
361 static void intel_smp_check(struct cpuinfo_x86 *c) in intel_smp_check() argument
364 if (!c->cpu_index) in intel_smp_check()
370 if (c->x86_vfm >= INTEL_FAM5_START && c->x86_vfm < INTEL_PENTIUM_MMX && in intel_smp_check()
371 c->x86_stepping >= 1 && c->x86_stepping <= 4) { in intel_smp_check()
388 static void intel_workarounds(struct cpuinfo_x86 *c) in intel_workarounds() argument
397 clear_cpu_bug(c, X86_BUG_F00F); in intel_workarounds()
398 if (c->x86_vfm >= INTEL_FAM5_START && c->x86_vfm < INTEL_QUARK_X1000) { in intel_workarounds()
401 set_cpu_bug(c, X86_BUG_F00F); in intel_workarounds()
413 if ((c->x86_vfm == INTEL_PENTIUM_II_KLAMATH && c->x86_stepping < 3) || in intel_workarounds()
414 c->x86_vfm < INTEL_PENTIUM_II_KLAMATH) in intel_workarounds()
415 clear_cpu_cap(c, X86_FEATURE_SEP); in intel_workarounds()
424 set_cpu_cap(c, X86_FEATURE_PAE); in intel_workarounds()
432 if (c->x86_vfm == INTEL_P4_WILLAMETTE && c->x86_stepping == 1) { in intel_workarounds()
446 if (boot_cpu_has(X86_FEATURE_APIC) && c->x86_vfm == INTEL_PENTIUM_75 && in intel_workarounds()
447 (c->x86_stepping < 0x6 || c->x86_stepping == 0xb)) in intel_workarounds()
448 set_cpu_bug(c, X86_BUG_11AP); in intel_workarounds()
458 if (c->x86_vfm >= INTEL_PENTIUM_PRO) in intel_workarounds()
462 intel_smp_check(c); in intel_workarounds()
465 static void intel_workarounds(struct cpuinfo_x86 *c) in intel_workarounds() argument
470 static void srat_detect_node(struct cpuinfo_x86 *c) in srat_detect_node() argument
487 static void init_cpuid_fault(struct cpuinfo_x86 *c) in init_cpuid_fault() argument
493 set_cpu_cap(c, X86_FEATURE_CPUID_FAULT); in init_cpuid_fault()
497 static void init_intel_misc_features(struct cpuinfo_x86 *c) in init_intel_misc_features() argument
508 init_cpuid_fault(c); in init_intel_misc_features()
509 probe_xeon_phi_r3mwait(c); in init_intel_misc_features()
534 static void init_intel(struct cpuinfo_x86 *c) in init_intel() argument
536 early_init_intel(c); in init_intel()
538 intel_workarounds(c); in init_intel()
540 init_intel_cacheinfo(c); in init_intel()
542 if (c->cpuid_level > 9) { in init_intel()
546 set_cpu_cap(c, X86_FEATURE_ARCH_PERFMON); in init_intel()
549 if (cpu_has(c, X86_FEATURE_XMM2)) in init_intel()
550 set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC); in init_intel()
557 set_cpu_cap(c, X86_FEATURE_BTS); in init_intel()
559 set_cpu_cap(c, X86_FEATURE_PEBS); in init_intel()
563 (c->x86_vfm == INTEL_CORE2_DUNNINGTON || in init_intel()
564 c->x86_vfm == INTEL_NEHALEM_EX || in init_intel()
565 c->x86_vfm == INTEL_WESTMERE_EX)) in init_intel()
566 set_cpu_bug(c, X86_BUG_CLFLUSH_MONITOR); in init_intel()
569 (c->x86_vfm == INTEL_ATOM_GOLDMONT || in init_intel()
570 c->x86_vfm == INTEL_LUNARLAKE_M)) in init_intel()
571 set_cpu_bug(c, X86_BUG_MONITOR); in init_intel()
574 if (c->x86 == 15) in init_intel()
575 c->x86_cache_alignment = c->x86_clflush_size * 2; in init_intel()
582 if (c->x86 == 6) { in init_intel()
583 unsigned int l2 = c->x86_cache_size; in init_intel()
586 switch (c->x86_model) { in init_intel()
597 else if (c->x86_stepping == 0 || c->x86_stepping == 5) in init_intel()
608 strcpy(c->x86_model_id, p); in init_intel()
613 set_cpu_cap(c, X86_FEATURE_PREFER_YMM); in init_intel()
616 srat_detect_node(c); in init_intel()
618 init_ia32_feat_ctl(c); in init_intel()
620 init_intel_misc_features(c); in init_intel()
624 intel_init_thermal(c); in init_intel()
628 static unsigned int intel_size_cache(struct cpuinfo_x86 *c, unsigned int size) in intel_size_cache() argument
636 if (c->x86_vfm == INTEL_PENTIUM_III_TUALATIN && size == 0) in intel_size_cache()
640 * Intel Quark SoC X1000 contains a 4-way set associative in intel_size_cache()
643 if (c->x86_vfm == INTEL_QUARK_X1000) in intel_size_cache()
674 * exception: it implies 4 dTLB entries for 1GB pages 32 dTLB entries
675 * for 2MB or 4MB pages. Encode descriptor 0x63 dTLB entry count for
676 * 2MB/4MB pages here, as its count for dTLB 1GB pages is already at the
688 { 0x01, TLB_INST_4K, 32}, /* TLB_INST 4 KByte pages, 4-way set associative */
689 { 0x02, TLB_INST_4M, 2}, /* TLB_INST 4 MByte pages, full associative */
690 { 0x03, TLB_DATA_4K, 64}, /* TLB_DATA 4 KByte pages, 4-way set associative */
691 { 0x04, TLB_DATA_4M, 8}, /* TLB_DATA 4 MByte pages, 4-way set associative */
692 { 0x05, TLB_DATA_4M, 32}, /* TLB_DATA 4 MByte pages, 4-way set associative */
693 { 0x0b, TLB_INST_4M, 4}, /* TLB_INST 4 MByte pages, 4-way set associative */
694 { 0x4f, TLB_INST_4K, 32}, /* TLB_INST 4 KByte pages */
695 { 0x50, TLB_INST_ALL, 64}, /* TLB_INST 4 KByte and 2-MByte or 4-MByte pages */
696 { 0x51, TLB_INST_ALL, 128}, /* TLB_INST 4 KByte and 2-MByte or 4-MByte pages */
697 { 0x52, TLB_INST_ALL, 256}, /* TLB_INST 4 KByte and 2-MByte or 4-MByte pages */
698 { 0x55, TLB_INST_2M_4M, 7}, /* TLB_INST 2-MByte or 4-MByte pages, fully associative */
699 { 0x56, TLB_DATA0_4M, 16}, /* TLB_DATA0 4 MByte pages, 4-way set associative */
700 { 0x57, TLB_DATA0_4K, 16}, /* TLB_DATA0 4 KByte pages, 4-way associative */
701 { 0x59, TLB_DATA0_4K, 16}, /* TLB_DATA0 4 KByte pages, fully associative */
702 { 0x5a, TLB_DATA0_2M_4M, 32}, /* TLB_DATA0 2-MByte or 4 MByte pages, 4-way set associative */
703 { 0x5b, TLB_DATA_4K_4M, 64}, /* TLB_DATA 4 KByte and 4 MByte pages */
704 { 0x5c, TLB_DATA_4K_4M, 128}, /* TLB_DATA 4 KByte and 4 MByte pages */
705 { 0x5d, TLB_DATA_4K_4M, 256}, /* TLB_DATA 4 KByte and 4 MByte pages */
706 { 0x61, TLB_INST_4K, 48}, /* TLB_INST 4 KByte pages, full associative */
707 { 0x63, TLB_DATA_1G_2M_4M, 4}, /* TLB_DATA 1 GByte pages, 4-way set associative
708 * (plus 32 entries TLB_DATA 2 MByte or 4 MByte pages, not encoded here) */
709 { 0x6b, TLB_DATA_4K, 256}, /* TLB_DATA 4 KByte pages, 8-way associative */
710 { 0x6c, TLB_DATA_2M_4M, 128}, /* TLB_DATA 2 MByte or 4 MByte pages, 8-way associative */
712 { 0x76, TLB_INST_2M_4M, 8}, /* TLB_INST 2-MByte or 4-MByte pages, fully associative */
713 { 0xb0, TLB_INST_4K, 128}, /* TLB_INST 4 KByte pages, 4-way set associative */
714 { 0xb1, TLB_INST_2M_4M, 4}, /* TLB_INST 2M pages, 4-way, 8 entries or 4M pages, 4-way entries */
715 { 0xb2, TLB_INST_4K, 64}, /* TLB_INST 4KByte pages, 4-way set associative */
716 { 0xb3, TLB_DATA_4K, 128}, /* TLB_DATA 4 KByte pages, 4-way set associative */
717 { 0xb4, TLB_DATA_4K, 256}, /* TLB_DATA 4 KByte pages, 4-way associative */
718 { 0xb5, TLB_INST_4K, 64}, /* TLB_INST 4 KByte pages, 8-way set associative */
719 { 0xb6, TLB_INST_4K, 128}, /* TLB_INST 4 KByte pages, 8-way set associative */
720 { 0xba, TLB_DATA_4K, 64}, /* TLB_DATA 4 KByte pages, 4-way associative */
721 { 0xc0, TLB_DATA_4K_4M, 8}, /* TLB_DATA 4 KByte and 4 MByte pages, 4-way associative */
722 { 0xc1, STLB_4K_2M, 1024}, /* STLB 4 KByte and 2 MByte pages, 8-way associative */
723 { 0xc2, TLB_DATA_2M_4M, 16}, /* TLB_DATA 2 MByte/4MByte pages, 4-way associative */
724 { 0xca, STLB_4K, 512}, /* STLB 4 KByte pages, 4-way associative */
800 static void intel_detect_tlb(struct cpuinfo_x86 *c) in intel_detect_tlb() argument
803 unsigned int regs[4]; in intel_detect_tlb()
806 if (c->cpuid_level < 2) in intel_detect_tlb()
816 for (j = 0 ; j < 4 ; j++) in intel_detect_tlb()
831 { .family = 4, .model_names =
837 [4] = "486 SL",
840 [8] = "486 DX/4",
841 [9] = "486 DX/4-WB"
850 [4] = "Pentium MMX",
861 [4] = "Pentium II (Deschutes)",
872 [0] = "Pentium 4 (Unknown)",
873 [1] = "Pentium 4 (Willamette)",
874 [2] = "Pentium 4 (Northwood)",
875 [4] = "Pentium 4 (Foster)",
876 [5] = "Pentium 4 (Foster)",