1 // SPDX-License-Identifier: GPL-2.0-only
13  *	Mikael Pettersson	:	Power Management for UP-APIC.
44 #include <asm/pc-conf-reg.h>
65 #include <asm/intel-family.h>
101  * Handle interrupt mode configuration register (IMCR).
104  * local APIC. Before entering Symmetric I/O Mode, either
106  * PIC Mode by changing the IMCR.
124  * +1=force-enable
214  * so apic->write/read doesn't do anything
242  * lapic_get_maxlvt - get the maximum number of local vector table entries
247 	 * - we always have APIC integrated on 64bit mode  in lapic_get_maxlvt()
248 	 * - 82489DXs do not report # of LVT entries  in lapic_get_maxlvt()
300 		 * See Intel SDM: TSC-Deadline Mode chapter. In xAPIC mode,  in __setup_APIC_LVTT()
392 		return -EINVAL;  in setup_APIC_eilvt()
400 		return -EBUSY;  in setup_APIC_eilvt()
437 	if (evt->features & CLOCK_EVT_FEAT_DUMMY)  in lapic_timer_shutdown()
463 	if (evt->features & CLOCK_EVT_FEAT_DUMMY)  in lapic_timer_set_periodic_oneshot()
507 	.irq				= -1,
556 	rev = (u32)m->driver_data;  in apic_validate_deadline_timer()
582 	levt->cpumask = cpumask_of(smp_processor_id());  in setup_APIC_timer()
585 		levt->name = "lapic-deadline";  in setup_APIC_timer()
586 		levt->features &= ~(CLOCK_EVT_FEAT_PERIODIC |  in setup_APIC_timer()
588 		levt->set_next_event = lapic_next_deadline;  in setup_APIC_timer()
613 	 * The clockevent device's ->mult and ->shift can both be  in lapic_update_tsc_freq()
643 static __initdata int lapic_cal_loops = -1;
689 	return -1;  in calibrate_by_pmtimer()
692 	apic_pr_verbose("... PM-Timer delta = %u\n", deltapm);  in calibrate_by_pmtimer()
696 		return -1;  in calibrate_by_pmtimer()
700 	if (deltapm > (pm_100ms - pm_thresh) &&  in calibrate_by_pmtimer()
702 		apic_pr_verbose("... PM-Timer result ok\n");  in calibrate_by_pmtimer()
708 	pr_warn("APIC calibration not consistent with PM-Timer: %ldms instead of 100ms\n",  in calibrate_by_pmtimer()
714 	pr_info("APIC delta adjusted to PM-Timer: "  in calibrate_by_pmtimer()
722 		apic_pr_verbose("TSC delta adjusted to PM-Timer: %lu (%ld)\n",  in calibrate_by_pmtimer()
733 		return -1;  in lapic_init_clockevent()
762 	 * If interrupt delivery mode is legacy PIC or virtual wire without  in apic_needs_pit()
853 				if ((tsc_now - tsc_start) >= tsc_perj) {  in calibrate_APIC_clock()
876 	/* Build delta t1-t2 as apic timer counts down */  in calibrate_APIC_clock()
877 	delta = lapic_cal_t1 - lapic_cal_t2;  in calibrate_APIC_clock()
880 	deltatsc = (long)(lapic_cal_tsc2 - lapic_cal_tsc1);  in calibrate_APIC_clock()
883 	pm_referenced = !calibrate_by_pmtimer(lapic_cal_pm2 - lapic_cal_pm1,  in calibrate_APIC_clock()
909 		return -1;  in calibrate_APIC_clock()
912 	levt->features &= ~CLOCK_EVT_FEAT_DUMMY;  in calibrate_APIC_clock()
925 		levt->event_handler = lapic_cal_handler;  in calibrate_APIC_clock()
927 		lapic_cal_loops = -1;  in calibrate_APIC_clock()
940 		deltaj = lapic_cal_j2 - lapic_cal_j1;  in calibrate_APIC_clock()
944 		if (deltaj >= LAPIC_CAL_LOOPS-2 && deltaj <= LAPIC_CAL_LOOPS+2)  in calibrate_APIC_clock()
947 			levt->features |= CLOCK_EVT_FEAT_DUMMY;  in calibrate_APIC_clock()
951 	if (levt->features & CLOCK_EVT_FEAT_DUMMY) {  in calibrate_APIC_clock()
953 		return -1;  in calibrate_APIC_clock()
1021 	 * its possible that when we get here evt->event_handler is NULL.  in local_apic_timer_interrupt()
1025 	if (!evt->event_handler) {  in local_apic_timer_interrupt()
1034 	 * the NMI deadlock-detector uses this.  in local_apic_timer_interrupt()
1038 	evt->event_handler(evt);  in local_apic_timer_interrupt()
1046  * [ if a single-CPU system runs an SMP kernel then we call the local
1066  * clear_local_APIC - shutdown the local APIC
1086 		v = ERROR_APIC_VECTOR; /* any non-zero vector will do */  in clear_local_APIC()
1091 	 * any level-triggered sources.  in clear_local_APIC()
1140  * apic_soft_disable - Clears and software disables the local APIC on hotplug
1143  * MSR_IA32_APICBASE. Clearing that bit on systems based on the 3 wire APIC
1163  * disable_local_APIC - clear and disable the local APIC
1189  * re-entering the BIOS on shutdown.  Otherwise the BIOS may get confused and
1190  * not power-off.  Additionally clear all LVT entries before disable_local_APIC
1214  * sync_Arb_IDs - synchronize APIC bus arbitration IDs
1219 	 * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not  in sync_Arb_IDs()
1246 	/* On 64-bit, the APIC must be integrated, Check local APIC only */  in __apic_intr_mode_select()
1253 	/* On 32-bit, the APIC may be integrated APIC or 82489DX */  in __apic_intr_mode_select()
1283 		pr_info("APIC: SMP mode deactivated\n");  in __apic_intr_mode_select()
1291 /* Select the interrupt delivery mode for the BSP */
1298  * An initial setup of the virtual wire mode.
1306 	 * through-I/O-APIC virtual wire mode might be active.  in init_bsp_APIC()
1335 	 * Set up the virtual wire mode.  in init_bsp_APIC()
1348 /* Init the interrupt delivery mode for the BSP */
1355 		pr_info("APIC: Keep in PIC mode(8259)\n");  in apic_intr_mode_init()
1358 		pr_info("APIC: Switch to virtual wire mode setup\n");  in apic_intr_mode_init()
1361 		pr_info("APIC: Switch to virtual wire mode setup with no configuration\n");  in apic_intr_mode_init()
1365 		pr_info("APIC: Switch to symmetric I/O mode setup\n");  in apic_intr_mode_init()
1368 		pr_info("APIC: Switch to symmetric I/O mode setup in no SMP routine\n");  in apic_intr_mode_init()
1389 	if (apic->disable_esr) {  in lapic_setup_esr()
1393 		 * ESR disabled - we can't do anything useful with the  in lapic_setup_esr()
1394 		 * errors anyway - mbligh  in lapic_setup_esr()
1436 		irr->regs[i] = apic_read(APIC_IRR + i * 0x10);  in apic_check_and_ack()
1440 		isr->regs[i] = apic_read(APIC_ISR + i * 0x10);  in apic_check_and_ack()
1447 	if (!bitmap_empty(isr->map, APIC_IR_BITS)) {  in apic_check_and_ack()
1453 		for_each_set_bit(bit, isr->map, APIC_IR_BITS)  in apic_check_and_ack()
1458 	return !bitmap_empty(irr->map, APIC_IR_BITS);  in apic_check_and_ack()
1490  * setup_local_APIC - setup the local APIC
1514 	/* Pound the ESR really hard over the head with a big hammer - mbligh */  in setup_local_APIC()
1515 	if (lapic_is_integrated() && apic->disable_esr) {  in setup_local_APIC()
1524 	 * an APIC.  See e.g. "AP-388 82489DX User's Manual" (Intel  in setup_local_APIC()
1527 	 * Except for APICs which operate in physical destination mode.  in setup_local_APIC()
1529 	if (apic->init_apic_ldr)  in setup_local_APIC()
1530 		apic->init_apic_ldr();  in setup_local_APIC()
1533 	 * Set Task Priority to 'accept all except vectors 0-31'.  An APIC  in setup_local_APIC()
1534 	 * vector in the 16-31 range could be delivered if TPR == 0, but we  in setup_local_APIC()
1564 	 * away, oh well :-(  in setup_local_APIC()
1566 	 * [ This bug can be reproduced easily with a level-triggered  in setup_local_APIC()
1573 	 * like LRU than MRU (the short-term load is more even across CPUs).  in setup_local_APIC()
1577 	 * - enable focus processor (bit==0)  in setup_local_APIC()
1578 	 * - 64bit mode always use processor focus  in setup_local_APIC()
1595 	 * set up through-local-APIC on the boot CPU's LINT0. This is not  in setup_local_APIC()
1596 	 * strictly necessary in pure symmetric-IO mode, but sometimes  in setup_local_APIC()
1600 	 * TODO: set up through-local-APIC from through-I/O-APIC? --macro  in setup_local_APIC()
1713 	/* Disable xapic and x2apic first and then reenable xapic mode */  in __x2apic_disable()
1741 			pr_warn("APIC locked in x2apic mode, can't disable\n");  in setup_nox2apic()
1830 			pr_info("x2apic: IRQ remapping doesn't support X2APIC mode\n");  in try_to_enable_x2apic()
1838 		 * used for non-remapped IRQ domains.  in try_to_enable_x2apic()
1847 		 * in physical mode, and CPUs with an APIC ID that cannot  in try_to_enable_x2apic()
1895 		pr_info("Not enabling interrupt remapping due to skipped IO-APIC setup\n");  in enable_IR_x2apic()
1905 		pr_info("Saving IO-APIC state failed: %d\n", ret);  in enable_IR_x2apic()
1910 	legacy_pic->mask_all();  in enable_IR_x2apic()
1916 	/* ir_stat contains the remap mode or an error code */  in enable_IR_x2apic()
1921 	legacy_pic->restore_mask();  in enable_IR_x2apic()
1927  * Detect and enable local APICs on non-SMP boards.
1929  * On AMD64 we trust the BIOS - if it says no APIC it is likely
1986 			pr_info("Local APIC disabled by BIOS -- reenabling.\n");  in apic_force_enable()
2024 		 * Over-ride BIOS and try to enable the local APIC only if  in detect_init_APIC()
2028 			pr_info("Local APIC disabled by BIOS -- "  in detect_init_APIC()
2050  * init_apic_mappings - initialize APIC mappings
2131  * spurious_interrupt - Catch all for interrupts raised on unused vectors
2168 	/* First tickle the hardware, only then report what went on. -- REW */  in DEFINE_IDTENTRY_SYSVEC()
2191  * connect_bsp_APIC - attach the APIC to the interrupt system
2202 		 * PIC mode, enable APIC mode in the IMCR, i.e.  connect BSP's  in connect_bsp_APIC()
2205 		apic_pr_verbose("Leaving PIC mode, enabling APIC mode.\n");  in connect_bsp_APIC()
2212  * disconnect_bsp_APIC - detach the APIC from the interrupt system
2213  * @virt_wire_setup:	indicates, whether virtual wire mode is selected
2215  * Virtual wire mode is necessary to deliver legacy interrupts even when the
2225 		 * Put the board back into PIC mode (has an effect only on  in disconnect_bsp_APIC()
2230 		apic_pr_verbose("Disabling APIC mode, entering PIC mode.\n");  in disconnect_bsp_APIC()
2236 	/* Go back to Virtual Wire compatibility mode */  in disconnect_bsp_APIC()
2280 	msg->arch_addr_lo.base_address = X86_MSI_BASE_ADDRESS_LOW;  in __irq_msi_compose_msg()
2281 	msg->arch_addr_lo.dest_mode_logical = apic->dest_mode_logical;  in __irq_msi_compose_msg()
2282 	msg->arch_addr_lo.destid_0_7 = cfg->dest_apicid & 0xFF;  in __irq_msi_compose_msg()
2284 	msg->arch_data.delivery_mode = APIC_DELIVERY_MODE_FIXED;  in __irq_msi_compose_msg()
2285 	msg->arch_data.vector = cfg->vector;  in __irq_msi_compose_msg()
2287 	msg->address_hi = X86_MSI_BASE_ADDRESS_HIGH;  in __irq_msi_compose_msg()
2292 	 * address APICs which can't be addressed in the normal 32-bit  in __irq_msi_compose_msg()
2295 	 * 5-11 to be used, giving support for 15 bits of APIC IDs in total.  in __irq_msi_compose_msg()
2298 		msg->arch_addr_hi.destid_8_31 = cfg->dest_apicid >> 8;  in __irq_msi_compose_msg()
2299 	else if (virt_ext_dest_id && cfg->dest_apicid < 0x8000)  in __irq_msi_compose_msg()
2300 		msg->arch_addr_lo.virt_destid_8_14 = cfg->dest_apicid >> 8;  in __irq_msi_compose_msg()
2302 		WARN_ON_ONCE(cfg->dest_apicid > 0xFF);  in __irq_msi_compose_msg()
2307 	u32 dest = msg->arch_addr_lo.destid_0_7;  in x86_msi_msg_get_destid()
2310 		dest |= msg->arch_addr_hi.destid_8_31 << 8;  in x86_msi_msg_get_destid()
2321  * apic_bsp_setup - Setup function for local apic and io-apic
2322  * @upmode:		Force UP mode (for APIC_init_uniprocessor)
2438 	 * IO-APIC and PIC have their own resume routines.  in lapic_resume()
2441 	 * and interrupt-remapping.  in lapic_resume()
2444 	legacy_pic->mask_all();  in lapic_resume()
2497  * This device has no shutdown method - fully functioning local APICs
2538 	pr_info("APIC: %s detected, Multi Chassis\n", d->ident);  in set_multi()
2565  * apic_is_clustered_box() -- Check if we can expect good TSC
2569  * multi-chassis.
2615 			return -EINVAL;  in apic_set_verbosity()
2629 		return -EINVAL;  in apic_set_verbosity()
2640 		return -1;  in lapic_insert_resource()
2644 	lapic_resource.end = lapic_resource.start + PAGE_SIZE - 1;  in lapic_insert_resource()
2659 		return -EINVAL;  in apic_set_extnmi()
2668 		pr_warn("Unknown external NMI delivery mode `%s' ignored\n", arg);  in apic_set_extnmi()
2669 		return -EINVAL;  in apic_set_extnmi()