Lines Matching +full:0 +full:x1c01
8 #define SNBEP_CPUNODEID 0x40
9 #define SNBEP_GIDNIDMAP 0x54
12 #define SNBEP_PMON_BOX_CTL_RST_CTRL (1 << 0)
20 #define SNBEP_PMON_CTL_EV_SEL_MASK 0x000000ff
21 #define SNBEP_PMON_CTL_UMASK_MASK 0x0000ff00
27 #define SNBEP_PMON_CTL_TRESH_MASK 0xff000000
35 #define SNBEP_U_MSR_PMON_CTL_TRESH_MASK 0x1f000000
48 #define SNBEP_PCU_MSR_PMON_CTL_OCC_SEL_MASK 0x0000c000
49 #define SNBEP_PCU_MSR_PMON_CTL_TRESH_MASK 0x1f000000
66 #define SNBEP_PCI_PMON_BOX_CTL 0xf4
67 #define SNBEP_PCI_PMON_CTL0 0xd8
69 #define SNBEP_PCI_PMON_CTR0 0xa0
72 #define SNBEP_HA_PCI_PMON_BOX_ADDRMATCH0 0x40
73 #define SNBEP_HA_PCI_PMON_BOX_ADDRMATCH1 0x44
74 #define SNBEP_HA_PCI_PMON_BOX_OPCODEMATCH 0x48
76 #define SNBEP_MC_CHy_PCI_PMON_FIXED_CTL 0xf0
77 #define SNBEP_MC_CHy_PCI_PMON_FIXED_CTR 0xd0
79 #define SNBEP_Q_Py_PCI_PMON_PKT_MATCH0 0x228
80 #define SNBEP_Q_Py_PCI_PMON_PKT_MATCH1 0x22c
81 #define SNBEP_Q_Py_PCI_PMON_PKT_MASK0 0x238
82 #define SNBEP_Q_Py_PCI_PMON_PKT_MASK1 0x23c
85 #define SNBEP_U_MSR_PMON_CTR0 0xc16
86 #define SNBEP_U_MSR_PMON_CTL0 0xc10
88 #define SNBEP_U_MSR_PMON_UCLK_FIXED_CTL 0xc08
89 #define SNBEP_U_MSR_PMON_UCLK_FIXED_CTR 0xc09
92 #define SNBEP_C0_MSR_PMON_CTR0 0xd16
93 #define SNBEP_C0_MSR_PMON_CTL0 0xd10
94 #define SNBEP_C0_MSR_PMON_BOX_CTL 0xd04
95 #define SNBEP_C0_MSR_PMON_BOX_FILTER 0xd14
96 #define SNBEP_CBO_MSR_OFFSET 0x20
98 #define SNBEP_CB0_MSR_PMON_BOX_FILTER_TID 0x1f
99 #define SNBEP_CB0_MSR_PMON_BOX_FILTER_NID 0x3fc00
100 #define SNBEP_CB0_MSR_PMON_BOX_FILTER_STATE 0x7c0000
101 #define SNBEP_CB0_MSR_PMON_BOX_FILTER_OPC 0xff800000
111 #define SNBEP_PCU_MSR_PMON_CTR0 0xc36
112 #define SNBEP_PCU_MSR_PMON_CTL0 0xc30
113 #define SNBEP_PCU_MSR_PMON_BOX_CTL 0xc24
114 #define SNBEP_PCU_MSR_PMON_BOX_FILTER 0xc34
115 #define SNBEP_PCU_MSR_PMON_BOX_FILTER_MASK 0xffffffff
116 #define SNBEP_PCU_MSR_CORE_C3_CTR 0x3fc
117 #define SNBEP_PCU_MSR_CORE_C6_CTR 0x3fd
127 #define IVBEP_U_MSR_PMON_GLOBAL_CTL 0xc00
140 #define IVBEP_CB0_MSR_PMON_BOX_FILTER_TID (0x1fULL << 0)
141 #define IVBEP_CB0_MSR_PMON_BOX_FILTER_LINK (0xfULL << 5)
142 #define IVBEP_CB0_MSR_PMON_BOX_FILTER_STATE (0x3fULL << 17)
143 #define IVBEP_CB0_MSR_PMON_BOX_FILTER_NID (0xffffULL << 32)
144 #define IVBEP_CB0_MSR_PMON_BOX_FILTER_OPC (0x1ffULL << 52)
145 #define IVBEP_CB0_MSR_PMON_BOX_FILTER_C6 (0x1ULL << 61)
146 #define IVBEP_CB0_MSR_PMON_BOX_FILTER_NC (0x1ULL << 62)
147 #define IVBEP_CB0_MSR_PMON_BOX_FILTER_ISOC (0x1ULL << 63)
171 #define HSWEP_U_MSR_PMON_CTR0 0x709
172 #define HSWEP_U_MSR_PMON_CTL0 0x705
173 #define HSWEP_U_MSR_PMON_FILTER 0x707
175 #define HSWEP_U_MSR_PMON_UCLK_FIXED_CTL 0x703
176 #define HSWEP_U_MSR_PMON_UCLK_FIXED_CTR 0x704
178 #define HSWEP_U_MSR_PMON_BOX_FILTER_TID (0x1 << 0)
179 #define HSWEP_U_MSR_PMON_BOX_FILTER_CID (0x1fULL << 1)
185 #define HSWEP_C0_MSR_PMON_CTR0 0xe08
186 #define HSWEP_C0_MSR_PMON_CTL0 0xe01
187 #define HSWEP_C0_MSR_PMON_BOX_CTL 0xe00
188 #define HSWEP_C0_MSR_PMON_BOX_FILTER0 0xe05
189 #define HSWEP_CBO_MSR_OFFSET 0x10
192 #define HSWEP_CB0_MSR_PMON_BOX_FILTER_TID (0x3fULL << 0)
193 #define HSWEP_CB0_MSR_PMON_BOX_FILTER_LINK (0xfULL << 6)
194 #define HSWEP_CB0_MSR_PMON_BOX_FILTER_STATE (0x7fULL << 17)
195 #define HSWEP_CB0_MSR_PMON_BOX_FILTER_NID (0xffffULL << 32)
196 #define HSWEP_CB0_MSR_PMON_BOX_FILTER_OPC (0x1ffULL << 52)
197 #define HSWEP_CB0_MSR_PMON_BOX_FILTER_C6 (0x1ULL << 61)
198 #define HSWEP_CB0_MSR_PMON_BOX_FILTER_NC (0x1ULL << 62)
199 #define HSWEP_CB0_MSR_PMON_BOX_FILTER_ISOC (0x1ULL << 63)
203 #define HSWEP_S0_MSR_PMON_CTR0 0x726
204 #define HSWEP_S0_MSR_PMON_CTL0 0x721
205 #define HSWEP_S0_MSR_PMON_BOX_CTL 0x720
206 #define HSWEP_SBOX_MSR_OFFSET 0xa
211 #define HSWEP_PCU_MSR_PMON_CTR0 0x717
212 #define HSWEP_PCU_MSR_PMON_CTL0 0x711
213 #define HSWEP_PCU_MSR_PMON_BOX_CTL 0x710
214 #define HSWEP_PCU_MSR_PMON_BOX_FILTER 0x715
221 #define KNL_CHA_MSR_OFFSET 0xc
226 #define KNL_CHA_MSR_PMON_BOX_FILTER_TID 0x1ff
228 #define KNL_CHA_MSR_PMON_BOX_FILTER_OP (0xfffffe2aULL << 32)
229 #define KNL_CHA_MSR_PMON_BOX_FILTER_REMOTE_NODE (0x1ULL << 32)
230 #define KNL_CHA_MSR_PMON_BOX_FILTER_LOCAL_NODE (0x1ULL << 33)
231 #define KNL_CHA_MSR_PMON_BOX_FILTER_NNC (0x1ULL << 37)
234 #define KNL_UCLK_MSR_PMON_CTR0_LOW 0x400
235 #define KNL_UCLK_MSR_PMON_CTL0 0x420
236 #define KNL_UCLK_MSR_PMON_BOX_CTL 0x430
237 #define KNL_UCLK_MSR_PMON_UCLK_FIXED_LOW 0x44c
238 #define KNL_UCLK_MSR_PMON_UCLK_FIXED_CTL 0x454
239 #define KNL_PMON_FIXED_CTL_EN 0x1
242 #define KNL_EDC0_ECLK_MSR_PMON_CTR0_LOW 0xa00
243 #define KNL_EDC0_ECLK_MSR_PMON_CTL0 0xa20
244 #define KNL_EDC0_ECLK_MSR_PMON_BOX_CTL 0xa30
245 #define KNL_EDC0_ECLK_MSR_PMON_ECLK_FIXED_LOW 0xa3c
246 #define KNL_EDC0_ECLK_MSR_PMON_ECLK_FIXED_CTL 0xa44
249 #define KNL_MC0_CH0_MSR_PMON_CTR0_LOW 0xb00
250 #define KNL_MC0_CH0_MSR_PMON_CTL0 0xb20
251 #define KNL_MC0_CH0_MSR_PMON_BOX_CTL 0xb30
252 #define KNL_MC0_CH0_MSR_PMON_FIXED_LOW 0xb3c
253 #define KNL_MC0_CH0_MSR_PMON_FIXED_CTL 0xb44
256 #define KNL_IRP_PCI_PMON_BOX_CTL 0xf0
260 #define KNL_PCU_PMON_CTL_EV_SEL_MASK 0x0000007f
262 #define KNL_PCU_MSR_PMON_CTL_TRESH_MASK 0x3f000000
275 #define SKX_CPUNODEID 0xc0
276 #define SKX_GIDNIDMAP 0xd4
295 * | [7:0] | 00h | BUS_NUM_0 - Return the bus number BIOS assigned
296 * CPUBUSNO(0). (RO)
298 #define SKX_MSR_CPU_BUS_NUMBER 0x300
303 #define SKX_CHA_MSR_PMON_BOX_FILTER_TID (0x1ffULL << 0)
304 #define SKX_CHA_MSR_PMON_BOX_FILTER_LINK (0xfULL << 9)
305 #define SKX_CHA_MSR_PMON_BOX_FILTER_STATE (0x3ffULL << 17)
306 #define SKX_CHA_MSR_PMON_BOX_FILTER_REM (0x1ULL << 32)
307 #define SKX_CHA_MSR_PMON_BOX_FILTER_LOC (0x1ULL << 33)
308 #define SKX_CHA_MSR_PMON_BOX_FILTER_ALL_OPC (0x1ULL << 35)
309 #define SKX_CHA_MSR_PMON_BOX_FILTER_NM (0x1ULL << 36)
310 #define SKX_CHA_MSR_PMON_BOX_FILTER_NOT_NM (0x1ULL << 37)
311 #define SKX_CHA_MSR_PMON_BOX_FILTER_OPC0 (0x3ffULL << 41)
312 #define SKX_CHA_MSR_PMON_BOX_FILTER_OPC1 (0x3ffULL << 51)
313 #define SKX_CHA_MSR_PMON_BOX_FILTER_C6 (0x1ULL << 61)
314 #define SKX_CHA_MSR_PMON_BOX_FILTER_NC (0x1ULL << 62)
315 #define SKX_CHA_MSR_PMON_BOX_FILTER_ISOC (0x1ULL << 63)
318 #define SKX_IIO0_MSR_PMON_CTL0 0xa48
319 #define SKX_IIO0_MSR_PMON_CTR0 0xa41
320 #define SKX_IIO0_MSR_PMON_BOX_CTL 0xa40
321 #define SKX_IIO_MSR_OFFSET 0x20
323 #define SKX_PMON_CTL_TRESH_MASK (0xff << 24)
324 #define SKX_PMON_CTL_TRESH_MASK_EXT (0xf)
325 #define SKX_PMON_CTL_CH_MASK (0xff << 4)
326 #define SKX_PMON_CTL_FC_MASK (0x7 << 12)
337 #define SKX_IRP0_MSR_PMON_CTL0 0xa5b
338 #define SKX_IRP0_MSR_PMON_CTR0 0xa59
339 #define SKX_IRP0_MSR_PMON_BOX_CTL 0xa58
340 #define SKX_IRP_MSR_OFFSET 0x20
343 #define SKX_UPI_PCI_PMON_CTL0 0x350
344 #define SKX_UPI_PCI_PMON_CTR0 0x318
345 #define SKX_UPI_PCI_PMON_BOX_CTL 0x378
346 #define SKX_UPI_CTL_UMASK_EXT 0xffefff
349 #define SKX_M2M_PCI_PMON_CTL0 0x228
350 #define SKX_M2M_PCI_PMON_CTR0 0x200
351 #define SKX_M2M_PCI_PMON_BOX_CTL 0x258
354 #define SNR_ICX_MESH2IIO_MMAP_DID 0x9a2
355 #define SNR_ICX_SAD_CONTROL_CFG 0x3f4
358 #define SAD_CONTROL_STACK_ID(data) (((data) >> 4) & 0x7)
361 #define SNR_U_MSR_PMON_CTR0 0x1f98
362 #define SNR_U_MSR_PMON_CTL0 0x1f91
363 #define SNR_U_MSR_PMON_UCLK_FIXED_CTL 0x1f93
364 #define SNR_U_MSR_PMON_UCLK_FIXED_CTR 0x1f94
367 #define SNR_CHA_RAW_EVENT_MASK_EXT 0x3ffffff
368 #define SNR_CHA_MSR_PMON_CTL0 0x1c01
369 #define SNR_CHA_MSR_PMON_CTR0 0x1c08
370 #define SNR_CHA_MSR_PMON_BOX_CTL 0x1c00
371 #define SNR_C0_MSR_PMON_BOX_FILTER0 0x1c05
375 #define SNR_IIO_MSR_PMON_CTL0 0x1e08
376 #define SNR_IIO_MSR_PMON_CTR0 0x1e01
377 #define SNR_IIO_MSR_PMON_BOX_CTL 0x1e00
378 #define SNR_IIO_MSR_OFFSET 0x10
379 #define SNR_IIO_PMON_RAW_EVENT_MASK_EXT 0x7ffff
382 #define SNR_IRP0_MSR_PMON_CTL0 0x1ea8
383 #define SNR_IRP0_MSR_PMON_CTR0 0x1ea1
384 #define SNR_IRP0_MSR_PMON_BOX_CTL 0x1ea0
385 #define SNR_IRP_MSR_OFFSET 0x10
388 #define SNR_M2PCIE_MSR_PMON_CTL0 0x1e58
389 #define SNR_M2PCIE_MSR_PMON_CTR0 0x1e51
390 #define SNR_M2PCIE_MSR_PMON_BOX_CTL 0x1e50
391 #define SNR_M2PCIE_MSR_OFFSET 0x10
394 #define SNR_PCU_MSR_PMON_CTL0 0x1ef1
395 #define SNR_PCU_MSR_PMON_CTR0 0x1ef8
396 #define SNR_PCU_MSR_PMON_BOX_CTL 0x1ef0
397 #define SNR_PCU_MSR_PMON_BOX_FILTER 0x1efc
400 #define SNR_M2M_PCI_PMON_CTL0 0x468
401 #define SNR_M2M_PCI_PMON_CTR0 0x440
402 #define SNR_M2M_PCI_PMON_BOX_CTL 0x438
403 #define SNR_M2M_PCI_PMON_UMASK_EXT 0xff
406 #define SNR_PCIE3_PCI_PMON_CTL0 0x508
407 #define SNR_PCIE3_PCI_PMON_CTR0 0x4e8
408 #define SNR_PCIE3_PCI_PMON_BOX_CTL 0x4e0
411 #define SNR_IMC_MMIO_PMON_FIXED_CTL 0x54
412 #define SNR_IMC_MMIO_PMON_FIXED_CTR 0x38
413 #define SNR_IMC_MMIO_PMON_CTL0 0x40
414 #define SNR_IMC_MMIO_PMON_CTR0 0x8
415 #define SNR_IMC_MMIO_PMON_BOX_CTL 0x22800
416 #define SNR_IMC_MMIO_OFFSET 0x4000
417 #define SNR_IMC_MMIO_SIZE 0x4000
418 #define SNR_IMC_MMIO_BASE_OFFSET 0xd0
419 #define SNR_IMC_MMIO_BASE_MASK 0x1FFFFFFF
420 #define SNR_IMC_MMIO_MEM0_OFFSET 0xd8
421 #define SNR_IMC_MMIO_MEM0_MASK 0x7FF
424 #define ICX_C34_MSR_PMON_CTR0 0xb68
425 #define ICX_C34_MSR_PMON_CTL0 0xb61
426 #define ICX_C34_MSR_PMON_BOX_CTL 0xb60
427 #define ICX_C34_MSR_PMON_BOX_FILTER0 0xb65
430 #define ICX_IIO_MSR_PMON_CTL0 0xa58
431 #define ICX_IIO_MSR_PMON_CTR0 0xa51
432 #define ICX_IIO_MSR_PMON_BOX_CTL 0xa50
435 #define ICX_IRP0_MSR_PMON_CTL0 0xa4d
436 #define ICX_IRP0_MSR_PMON_CTR0 0xa4b
437 #define ICX_IRP0_MSR_PMON_BOX_CTL 0xa4a
440 #define ICX_M2PCIE_MSR_PMON_CTL0 0xa46
441 #define ICX_M2PCIE_MSR_PMON_CTR0 0xa41
442 #define ICX_M2PCIE_MSR_PMON_BOX_CTL 0xa40
445 #define ICX_UPI_PCI_PMON_CTL0 0x350
446 #define ICX_UPI_PCI_PMON_CTR0 0x320
447 #define ICX_UPI_PCI_PMON_BOX_CTL 0x318
448 #define ICX_UPI_CTL_UMASK_EXT 0xffffff
449 #define ICX_UBOX_DID 0x3450
452 #define ICX_M3UPI_PCI_PMON_CTL0 0xd8
453 #define ICX_M3UPI_PCI_PMON_CTR0 0xa8
454 #define ICX_M3UPI_PCI_PMON_BOX_CTL 0xa0
458 #define ICX_IMC_MEM_STRIDE 0x4
461 #define SPR_RAW_EVENT_MASK_EXT 0xffffff
462 #define SPR_UBOX_DID 0x3250
465 #define SPR_CHA_EVENT_MASK_EXT 0xffffffff
469 #define SPR_CHA_PMON_BOX_FILTER_TID 0x3ff
471 #define SPR_C0_MSR_PMON_BOX_FILTER0 0x200e
473 DEFINE_UNCORE_FORMAT_ATTR(event, event, "config:0-7");
474 DEFINE_UNCORE_FORMAT_ATTR(event2, event, "config:0-6");
475 DEFINE_UNCORE_FORMAT_ATTR(event_ext, event, "config:0-7,21");
500 DEFINE_UNCORE_FORMAT_ATTR(filter_tid, filter_tid, "config1:0-4");
501 DEFINE_UNCORE_FORMAT_ATTR(filter_tid2, filter_tid, "config1:0");
502 DEFINE_UNCORE_FORMAT_ATTR(filter_tid3, filter_tid, "config1:0-5");
503 DEFINE_UNCORE_FORMAT_ATTR(filter_tid4, filter_tid, "config1:0-8");
504 DEFINE_UNCORE_FORMAT_ATTR(filter_tid5, filter_tid, "config1:0-9");
531 DEFINE_UNCORE_FORMAT_ATTR(filter_band0, filter_band0, "config1:0-7");
542 DEFINE_UNCORE_FORMAT_ATTR(match0, match0, "config1:0-31");
551 DEFINE_UNCORE_FORMAT_ATTR(mask0, mask0, "config2:0-31");
558 u32 config = 0; in snbep_uncore_pci_disable_box()
570 u32 config = 0; in snbep_uncore_pci_enable_box()
598 u64 count = 0; in snbep_uncore_pci_read_counter()
646 wrmsrl(reg1->reg, uncore_shared_reg_config(box, 0)); in snbep_uncore_msr_enable_event()
742 INTEL_UNCORE_EVENT_DESC(clockticks, "event=0xff,umask=0x00"),
743 INTEL_UNCORE_EVENT_DESC(cas_count_read, "event=0x04,umask=0x03"),
746 INTEL_UNCORE_EVENT_DESC(cas_count_write, "event=0x04,umask=0x0c"),
753 INTEL_UNCORE_EVENT_DESC(clockticks, "event=0x14"),
754 INTEL_UNCORE_EVENT_DESC(txl_flits_active, "event=0x00,umask=0x06"),
755 INTEL_UNCORE_EVENT_DESC(drs_data, "event=0x102,umask=0x08"),
756 INTEL_UNCORE_EVENT_DESC(ncb_data, "event=0x103,umask=0x04"),
813 UNCORE_EVENT_CONSTRAINT(0x01, 0x1),
814 UNCORE_EVENT_CONSTRAINT(0x02, 0x3),
815 UNCORE_EVENT_CONSTRAINT(0x04, 0x3),
816 UNCORE_EVENT_CONSTRAINT(0x05, 0x3),
817 UNCORE_EVENT_CONSTRAINT(0x07, 0x3),
818 UNCORE_EVENT_CONSTRAINT(0x09, 0x3),
819 UNCORE_EVENT_CONSTRAINT(0x11, 0x1),
820 UNCORE_EVENT_CONSTRAINT(0x12, 0x3),
821 UNCORE_EVENT_CONSTRAINT(0x13, 0x3),
822 UNCORE_EVENT_CONSTRAINT(0x1b, 0xc),
823 UNCORE_EVENT_CONSTRAINT(0x1c, 0xc),
824 UNCORE_EVENT_CONSTRAINT(0x1d, 0xc),
825 UNCORE_EVENT_CONSTRAINT(0x1e, 0xc),
826 UNCORE_EVENT_CONSTRAINT(0x1f, 0xe),
827 UNCORE_EVENT_CONSTRAINT(0x21, 0x3),
828 UNCORE_EVENT_CONSTRAINT(0x23, 0x3),
829 UNCORE_EVENT_CONSTRAINT(0x31, 0x3),
830 UNCORE_EVENT_CONSTRAINT(0x32, 0x3),
831 UNCORE_EVENT_CONSTRAINT(0x33, 0x3),
832 UNCORE_EVENT_CONSTRAINT(0x34, 0x3),
833 UNCORE_EVENT_CONSTRAINT(0x35, 0x3),
834 UNCORE_EVENT_CONSTRAINT(0x36, 0x1),
835 UNCORE_EVENT_CONSTRAINT(0x37, 0x3),
836 UNCORE_EVENT_CONSTRAINT(0x38, 0x3),
837 UNCORE_EVENT_CONSTRAINT(0x39, 0x3),
838 UNCORE_EVENT_CONSTRAINT(0x3b, 0x1),
843 UNCORE_EVENT_CONSTRAINT(0x10, 0x3),
844 UNCORE_EVENT_CONSTRAINT(0x11, 0x3),
845 UNCORE_EVENT_CONSTRAINT(0x12, 0x1),
846 UNCORE_EVENT_CONSTRAINT(0x23, 0x3),
847 UNCORE_EVENT_CONSTRAINT(0x24, 0x3),
848 UNCORE_EVENT_CONSTRAINT(0x25, 0x3),
849 UNCORE_EVENT_CONSTRAINT(0x26, 0x3),
850 UNCORE_EVENT_CONSTRAINT(0x32, 0x3),
851 UNCORE_EVENT_CONSTRAINT(0x33, 0x3),
852 UNCORE_EVENT_CONSTRAINT(0x34, 0x3),
857 UNCORE_EVENT_CONSTRAINT(0x10, 0x3),
858 UNCORE_EVENT_CONSTRAINT(0x11, 0x3),
859 UNCORE_EVENT_CONSTRAINT(0x12, 0x3),
860 UNCORE_EVENT_CONSTRAINT(0x13, 0x1),
861 UNCORE_EVENT_CONSTRAINT(0x20, 0x3),
862 UNCORE_EVENT_CONSTRAINT(0x21, 0x3),
863 UNCORE_EVENT_CONSTRAINT(0x22, 0x3),
864 UNCORE_EVENT_CONSTRAINT(0x23, 0x3),
865 UNCORE_EVENT_CONSTRAINT(0x24, 0x3),
866 UNCORE_EVENT_CONSTRAINT(0x25, 0x3),
867 UNCORE_EVENT_CONSTRAINT(0x26, 0x3),
868 UNCORE_EVENT_CONSTRAINT(0x28, 0x3),
869 UNCORE_EVENT_CONSTRAINT(0x29, 0x3),
870 UNCORE_EVENT_CONSTRAINT(0x2a, 0x3),
871 UNCORE_EVENT_CONSTRAINT(0x2b, 0x3),
872 UNCORE_EVENT_CONSTRAINT(0x2c, 0x3),
873 UNCORE_EVENT_CONSTRAINT(0x2d, 0x3),
874 UNCORE_EVENT_CONSTRAINT(0x2e, 0x3),
875 UNCORE_EVENT_CONSTRAINT(0x2f, 0x3),
876 UNCORE_EVENT_CONSTRAINT(0x30, 0x3),
877 UNCORE_EVENT_CONSTRAINT(0x31, 0x3),
878 UNCORE_EVENT_CONSTRAINT(0x32, 0x3),
879 UNCORE_EVENT_CONSTRAINT(0x33, 0x3),
880 UNCORE_EVENT_CONSTRAINT(0x34, 0x3),
881 UNCORE_EVENT_CONSTRAINT(0x36, 0x3),
882 UNCORE_EVENT_CONSTRAINT(0x37, 0x3),
883 UNCORE_EVENT_CONSTRAINT(0x38, 0x3),
884 UNCORE_EVENT_CONSTRAINT(0x39, 0x3),
905 SNBEP_CBO_PMON_CTL_TID_EN, 0x1),
906 SNBEP_CBO_EVENT_EXTRA_REG(0x0334, 0xffff, 0x4),
907 SNBEP_CBO_EVENT_EXTRA_REG(0x4334, 0xffff, 0x6),
908 SNBEP_CBO_EVENT_EXTRA_REG(0x0534, 0xffff, 0x4),
909 SNBEP_CBO_EVENT_EXTRA_REG(0x4534, 0xffff, 0x6),
910 SNBEP_CBO_EVENT_EXTRA_REG(0x0934, 0xffff, 0x4),
911 SNBEP_CBO_EVENT_EXTRA_REG(0x4934, 0xffff, 0x6),
912 SNBEP_CBO_EVENT_EXTRA_REG(0x4134, 0xffff, 0x6),
913 SNBEP_CBO_EVENT_EXTRA_REG(0x0135, 0xffff, 0x8),
914 SNBEP_CBO_EVENT_EXTRA_REG(0x0335, 0xffff, 0x8),
915 SNBEP_CBO_EVENT_EXTRA_REG(0x4135, 0xffff, 0xa),
916 SNBEP_CBO_EVENT_EXTRA_REG(0x4335, 0xffff, 0xa),
917 SNBEP_CBO_EVENT_EXTRA_REG(0x4435, 0xffff, 0x2),
918 SNBEP_CBO_EVENT_EXTRA_REG(0x4835, 0xffff, 0x2),
919 SNBEP_CBO_EVENT_EXTRA_REG(0x4a35, 0xffff, 0x2),
920 SNBEP_CBO_EVENT_EXTRA_REG(0x5035, 0xffff, 0x2),
921 SNBEP_CBO_EVENT_EXTRA_REG(0x0136, 0xffff, 0x8),
922 SNBEP_CBO_EVENT_EXTRA_REG(0x0336, 0xffff, 0x8),
923 SNBEP_CBO_EVENT_EXTRA_REG(0x4136, 0xffff, 0xa),
924 SNBEP_CBO_EVENT_EXTRA_REG(0x4336, 0xffff, 0xa),
925 SNBEP_CBO_EVENT_EXTRA_REG(0x4436, 0xffff, 0x2),
926 SNBEP_CBO_EVENT_EXTRA_REG(0x4836, 0xffff, 0x2),
927 SNBEP_CBO_EVENT_EXTRA_REG(0x4a36, 0xffff, 0x2),
928 SNBEP_CBO_EVENT_EXTRA_REG(0x4037, 0x40ff, 0x2),
935 struct intel_uncore_extra_reg *er = &box->shared_regs[0]; in snbep_cbox_put_constraint()
941 for (i = 0; i < 5; i++) { in snbep_cbox_put_constraint()
942 if (reg1->alloc & (0x1 << i)) in snbep_cbox_put_constraint()
945 reg1->alloc = 0; in snbep_cbox_put_constraint()
953 struct intel_uncore_extra_reg *er = &box->shared_regs[0]; in __snbep_cbox_get_constraint()
954 int i, alloc = 0; in __snbep_cbox_get_constraint()
962 for (i = 0; i < 5; i++) { in __snbep_cbox_get_constraint()
963 if (!(reg1->idx & (0x1 << i))) in __snbep_cbox_get_constraint()
965 if (!uncore_box_is_fake(box) && (reg1->alloc & (0x1 << i))) in __snbep_cbox_get_constraint()
968 mask = cbox_filter_mask(0x1 << i); in __snbep_cbox_get_constraint()
974 alloc |= (0x1 << i); in __snbep_cbox_get_constraint()
988 for (; i >= 0; i--) { in __snbep_cbox_get_constraint()
989 if (alloc & (0x1 << i)) in __snbep_cbox_get_constraint()
997 u64 mask = 0; in snbep_cbox_filter_mask()
999 if (fields & 0x1) in snbep_cbox_filter_mask()
1001 if (fields & 0x2) in snbep_cbox_filter_mask()
1003 if (fields & 0x4) in snbep_cbox_filter_mask()
1005 if (fields & 0x8) in snbep_cbox_filter_mask()
1021 int idx = 0; in snbep_cbox_hw_config()
1035 return 0; in snbep_cbox_hw_config()
1084 struct intel_uncore_extra_reg *er = &box->shared_regs[0]; in snbep_pcu_get_constraint()
1094 mask = 0xffULL << (idx * 8); in snbep_pcu_get_constraint()
1125 struct intel_uncore_extra_reg *er = &box->shared_regs[0]; in snbep_pcu_put_constraint()
1131 reg1->alloc = 0; in snbep_pcu_put_constraint()
1140 if (ev_sel >= 0xb && ev_sel <= 0xe) { in snbep_pcu_hw_config()
1142 reg1->idx = ev_sel - 0xb; in snbep_pcu_hw_config()
1143 reg1->config = event->attr.config1 & (0xff << (reg1->idx * 8)); in snbep_pcu_hw_config()
1145 return 0; in snbep_pcu_hw_config()
1195 if ((hwc->config & SNBEP_PMON_CTL_EV_SEL_MASK) == 0x38) { in snbep_qpi_hw_config()
1196 reg1->idx = 0; in snbep_qpi_hw_config()
1202 return 0; in snbep_qpi_hw_config()
1322 .driver_data = UNCORE_PCI_DEV_DATA(SNBEP_PCI_UNCORE_HA, 0),
1324 { /* MC Channel 0 */
1326 .driver_data = UNCORE_PCI_DEV_DATA(SNBEP_PCI_UNCORE_IMC, 0),
1340 { /* QPI Port 0 */
1342 .driver_data = UNCORE_PCI_DEV_DATA(SNBEP_PCI_UNCORE_QPI, 0),
1350 .driver_data = UNCORE_PCI_DEV_DATA(SNBEP_PCI_UNCORE_R2PCIE, 0),
1352 { /* R3QPI Link 0 */
1354 .driver_data = UNCORE_PCI_DEV_DATA(SNBEP_PCI_UNCORE_R3QPI, 0),
1360 { /* QPI Port 0 filter */
1361 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x3c86),
1365 { /* QPI Port 0 filter */
1366 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x3c96),
1378 #define NODE_ID_MASK 0x7
1380 /* Each three bits from 0 to 23 of GIDNIDMAP register correspond Node ID. */
1381 #define GIDNIDMAP(config, id) (((config) >> (3 * (id))) & 0x7)
1410 for (i = 0; i < 8; i++) { in topology_gidnid_map()
1416 if (die_id < 0) in topology_gidnid_map()
1433 int err = 0; in snbep_pci2phy_map_init()
1434 u32 config = 0; in snbep_pci2phy_map_init()
1496 for (bus = 255; bus >= 0; bus--) { in snbep_pci2phy_map_init()
1503 for (bus = 0; bus <= 255; bus++) { in snbep_pci2phy_map_init()
1521 int ret = snbep_pci2phy_map_init(0x3ce0, SNBEP_CPUNODEID, SNBEP_GIDNIDMAP, true); in snbep_uncore_pci_init()
1526 return 0; in snbep_uncore_pci_init()
1691 SNBEP_CBO_PMON_CTL_TID_EN, 0x1),
1692 SNBEP_CBO_EVENT_EXTRA_REG(0x1031, 0x10ff, 0x2),
1693 SNBEP_CBO_EVENT_EXTRA_REG(0x1134, 0xffff, 0x4),
1694 SNBEP_CBO_EVENT_EXTRA_REG(0x4134, 0xffff, 0xc),
1695 SNBEP_CBO_EVENT_EXTRA_REG(0x5134, 0xffff, 0xc),
1696 SNBEP_CBO_EVENT_EXTRA_REG(0x0334, 0xffff, 0x4),
1697 SNBEP_CBO_EVENT_EXTRA_REG(0x4334, 0xffff, 0xc),
1698 SNBEP_CBO_EVENT_EXTRA_REG(0x0534, 0xffff, 0x4),
1699 SNBEP_CBO_EVENT_EXTRA_REG(0x4534, 0xffff, 0xc),
1700 SNBEP_CBO_EVENT_EXTRA_REG(0x0934, 0xffff, 0x4),
1701 SNBEP_CBO_EVENT_EXTRA_REG(0x4934, 0xffff, 0xc),
1702 SNBEP_CBO_EVENT_EXTRA_REG(0x0135, 0xffff, 0x10),
1703 SNBEP_CBO_EVENT_EXTRA_REG(0x0335, 0xffff, 0x10),
1704 SNBEP_CBO_EVENT_EXTRA_REG(0x2135, 0xffff, 0x10),
1705 SNBEP_CBO_EVENT_EXTRA_REG(0x2335, 0xffff, 0x10),
1706 SNBEP_CBO_EVENT_EXTRA_REG(0x4135, 0xffff, 0x18),
1707 SNBEP_CBO_EVENT_EXTRA_REG(0x4335, 0xffff, 0x18),
1708 SNBEP_CBO_EVENT_EXTRA_REG(0x4435, 0xffff, 0x8),
1709 SNBEP_CBO_EVENT_EXTRA_REG(0x4835, 0xffff, 0x8),
1710 SNBEP_CBO_EVENT_EXTRA_REG(0x4a35, 0xffff, 0x8),
1711 SNBEP_CBO_EVENT_EXTRA_REG(0x5035, 0xffff, 0x8),
1712 SNBEP_CBO_EVENT_EXTRA_REG(0x8135, 0xffff, 0x10),
1713 SNBEP_CBO_EVENT_EXTRA_REG(0x8335, 0xffff, 0x10),
1714 SNBEP_CBO_EVENT_EXTRA_REG(0x0136, 0xffff, 0x10),
1715 SNBEP_CBO_EVENT_EXTRA_REG(0x0336, 0xffff, 0x10),
1716 SNBEP_CBO_EVENT_EXTRA_REG(0x2136, 0xffff, 0x10),
1717 SNBEP_CBO_EVENT_EXTRA_REG(0x2336, 0xffff, 0x10),
1718 SNBEP_CBO_EVENT_EXTRA_REG(0x4136, 0xffff, 0x18),
1719 SNBEP_CBO_EVENT_EXTRA_REG(0x4336, 0xffff, 0x18),
1720 SNBEP_CBO_EVENT_EXTRA_REG(0x4436, 0xffff, 0x8),
1721 SNBEP_CBO_EVENT_EXTRA_REG(0x4836, 0xffff, 0x8),
1722 SNBEP_CBO_EVENT_EXTRA_REG(0x4a36, 0xffff, 0x8),
1723 SNBEP_CBO_EVENT_EXTRA_REG(0x5036, 0xffff, 0x8),
1724 SNBEP_CBO_EVENT_EXTRA_REG(0x8136, 0xffff, 0x10),
1725 SNBEP_CBO_EVENT_EXTRA_REG(0x8336, 0xffff, 0x10),
1726 SNBEP_CBO_EVENT_EXTRA_REG(0x4037, 0x40ff, 0x8),
1732 u64 mask = 0; in ivbep_cbox_filter_mask()
1734 if (fields & 0x1) in ivbep_cbox_filter_mask()
1736 if (fields & 0x2) in ivbep_cbox_filter_mask()
1738 if (fields & 0x4) in ivbep_cbox_filter_mask()
1740 if (fields & 0x8) in ivbep_cbox_filter_mask()
1742 if (fields & 0x10) { in ivbep_cbox_filter_mask()
1762 int idx = 0; in ivbep_cbox_hw_config()
1776 return 0; in ivbep_cbox_hw_config()
1785 u64 filter = uncore_shared_reg_config(box, 0); in ivbep_cbox_enable_event()
1786 wrmsrl(reg1->reg, filter & 0xffffffff); in ivbep_cbox_enable_event()
1877 static unsigned ivbep_uncore_irp_ctls[] = {0xd8, 0xdc, 0xe0, 0xe4};
1878 static unsigned ivbep_uncore_irp_ctrs[] = {0xa0, 0xb0, 0xb8, 0xc0};
1901 u64 count = 0; in ivbep_uncore_irp_read_counter()
1993 { /* Home Agent 0 */
1994 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xe30),
1995 .driver_data = UNCORE_PCI_DEV_DATA(IVBEP_PCI_UNCORE_HA, 0),
1998 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xe38),
2001 { /* MC0 Channel 0 */
2002 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xeb4),
2003 .driver_data = UNCORE_PCI_DEV_DATA(IVBEP_PCI_UNCORE_IMC, 0),
2006 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xeb5),
2010 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xeb0),
2014 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xeb1),
2017 { /* MC1 Channel 0 */
2018 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xef4),
2022 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xef5),
2026 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xef0),
2030 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xef1),
2034 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xe39),
2035 .driver_data = UNCORE_PCI_DEV_DATA(IVBEP_PCI_UNCORE_IRP, 0),
2037 { /* QPI0 Port 0 */
2038 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xe32),
2039 .driver_data = UNCORE_PCI_DEV_DATA(IVBEP_PCI_UNCORE_QPI, 0),
2042 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xe33),
2046 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xe3a),
2050 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xe34),
2051 .driver_data = UNCORE_PCI_DEV_DATA(IVBEP_PCI_UNCORE_R2PCIE, 0),
2053 { /* R3QPI0 Link 0 */
2054 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xe36),
2055 .driver_data = UNCORE_PCI_DEV_DATA(IVBEP_PCI_UNCORE_R3QPI, 0),
2058 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xe37),
2062 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xe3e),
2065 { /* QPI Port 0 filter */
2066 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xe86),
2070 { /* QPI Port 0 filter */
2071 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xe96),
2085 int ret = snbep_pci2phy_map_init(0x0e1e, SNBEP_CPUNODEID, SNBEP_GIDNIDMAP, true); in ivbep_uncore_pci_init()
2090 return 0; in ivbep_uncore_pci_init()
2151 UNCORE_EVENT_CONSTRAINT(0x11, 0x1),
2152 UNCORE_EVENT_CONSTRAINT(0x1f, 0x1),
2153 UNCORE_EVENT_CONSTRAINT(0x36, 0x1),
2159 SNBEP_CBO_PMON_CTL_TID_EN, 0x1),
2160 SNBEP_CBO_EVENT_EXTRA_REG(0x3d, 0xff, 0x2),
2161 SNBEP_CBO_EVENT_EXTRA_REG(0x35, 0xff, 0x4),
2162 SNBEP_CBO_EVENT_EXTRA_REG(0x36, 0xff, 0x4),
2168 u64 mask = 0; in knl_cha_filter_mask()
2170 if (fields & 0x1) in knl_cha_filter_mask()
2172 if (fields & 0x2) in knl_cha_filter_mask()
2174 if (fields & 0x4) in knl_cha_filter_mask()
2190 int idx = 0; in knl_cha_hw_config()
2208 return 0; in knl_cha_hw_config()
2290 pci_write_config_dword(pdev, box_ctl, 0); in knl_uncore_imc_enable_box()
2382 UNCORE_EVENT_CONSTRAINT(0x23, 0x3),
2449 * 0x7841 MC0 UClk, MC1 UClk
2450 * 0x7843 MC0 DClk CH 0, MC0 DClk CH 1, MC0 DClk CH 2,
2451 * MC1 DClk CH 0, MC1 DClk CH 1, MC1 DClk CH 2
2452 * 0x7833 EDC0 UClk, EDC1 UClk, EDC2 UClk, EDC3 UClk,
2454 * 0x7835 EDC0 EClk, EDC1 EClk, EDC2 EClk, EDC3 EClk,
2456 * 0x7817 M2PCIe
2457 * 0x7814 IRP
2462 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x7841),
2463 .driver_data = UNCORE_PCI_DEV_FULL_DATA(10, 0, KNL_PCI_UNCORE_MC_UCLK, 0),
2466 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x7841),
2467 .driver_data = UNCORE_PCI_DEV_FULL_DATA(11, 0, KNL_PCI_UNCORE_MC_UCLK, 1),
2469 { /* MC0 DClk CH 0 */
2470 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x7843),
2471 .driver_data = UNCORE_PCI_DEV_FULL_DATA(8, 2, KNL_PCI_UNCORE_MC_DCLK, 0),
2474 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x7843),
2478 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x7843),
2481 { /* MC1 DClk CH 0 */
2482 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x7843),
2486 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x7843),
2490 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x7843),
2494 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x7833),
2495 .driver_data = UNCORE_PCI_DEV_FULL_DATA(15, 0, KNL_PCI_UNCORE_EDC_UCLK, 0),
2498 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x7833),
2499 .driver_data = UNCORE_PCI_DEV_FULL_DATA(16, 0, KNL_PCI_UNCORE_EDC_UCLK, 1),
2502 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x7833),
2503 .driver_data = UNCORE_PCI_DEV_FULL_DATA(17, 0, KNL_PCI_UNCORE_EDC_UCLK, 2),
2506 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x7833),
2507 .driver_data = UNCORE_PCI_DEV_FULL_DATA(18, 0, KNL_PCI_UNCORE_EDC_UCLK, 3),
2510 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x7833),
2511 .driver_data = UNCORE_PCI_DEV_FULL_DATA(19, 0, KNL_PCI_UNCORE_EDC_UCLK, 4),
2514 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x7833),
2515 .driver_data = UNCORE_PCI_DEV_FULL_DATA(20, 0, KNL_PCI_UNCORE_EDC_UCLK, 5),
2518 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x7833),
2519 .driver_data = UNCORE_PCI_DEV_FULL_DATA(21, 0, KNL_PCI_UNCORE_EDC_UCLK, 6),
2522 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x7833),
2523 .driver_data = UNCORE_PCI_DEV_FULL_DATA(22, 0, KNL_PCI_UNCORE_EDC_UCLK, 7),
2526 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x7835),
2527 .driver_data = UNCORE_PCI_DEV_FULL_DATA(24, 2, KNL_PCI_UNCORE_EDC_ECLK, 0),
2530 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x7835),
2534 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x7835),
2538 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x7835),
2542 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x7835),
2546 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x7835),
2550 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x7835),
2554 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x7835),
2558 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x7817),
2559 .driver_data = UNCORE_PCI_DEV_DATA(KNL_PCI_UNCORE_M2PCIE, 0),
2562 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x7814),
2563 .driver_data = UNCORE_PCI_DEV_DATA(KNL_PCI_UNCORE_IRP, 0),
2578 ret = snb_pci2phy_map_init(0x7814); /* IRP */ in knl_uncore_pci_init()
2581 ret = snb_pci2phy_map_init(0x7817); /* M2PCIe */ in knl_uncore_pci_init()
2586 return 0; in knl_uncore_pci_init()
2613 reg1->idx = 0; in hswep_ubox_hw_config()
2614 return 0; in hswep_ubox_hw_config()
2663 UNCORE_EVENT_CONSTRAINT(0x01, 0x1),
2664 UNCORE_EVENT_CONSTRAINT(0x09, 0x1),
2665 UNCORE_EVENT_CONSTRAINT(0x11, 0x1),
2666 UNCORE_EVENT_CONSTRAINT(0x36, 0x1),
2667 UNCORE_EVENT_CONSTRAINT(0x38, 0x3),
2668 UNCORE_EVENT_CONSTRAINT(0x3b, 0x1),
2669 UNCORE_EVENT_CONSTRAINT(0x3e, 0x1),
2675 SNBEP_CBO_PMON_CTL_TID_EN, 0x1),
2676 SNBEP_CBO_EVENT_EXTRA_REG(0x0334, 0xffff, 0x4),
2677 SNBEP_CBO_EVENT_EXTRA_REG(0x0534, 0xffff, 0x4),
2678 SNBEP_CBO_EVENT_EXTRA_REG(0x0934, 0xffff, 0x4),
2679 SNBEP_CBO_EVENT_EXTRA_REG(0x1134, 0xffff, 0x4),
2680 SNBEP_CBO_EVENT_EXTRA_REG(0x2134, 0xffff, 0x4),
2681 SNBEP_CBO_EVENT_EXTRA_REG(0x4134, 0xffff, 0x4),
2682 SNBEP_CBO_EVENT_EXTRA_REG(0x4037, 0x40ff, 0x8),
2683 SNBEP_CBO_EVENT_EXTRA_REG(0x4028, 0x40ff, 0x8),
2684 SNBEP_CBO_EVENT_EXTRA_REG(0x4032, 0x40ff, 0x8),
2685 SNBEP_CBO_EVENT_EXTRA_REG(0x4029, 0x40ff, 0x8),
2686 SNBEP_CBO_EVENT_EXTRA_REG(0x4033, 0x40ff, 0x8),
2687 SNBEP_CBO_EVENT_EXTRA_REG(0x402A, 0x40ff, 0x8),
2688 SNBEP_CBO_EVENT_EXTRA_REG(0x0135, 0xffff, 0x12),
2689 SNBEP_CBO_EVENT_EXTRA_REG(0x0335, 0xffff, 0x10),
2690 SNBEP_CBO_EVENT_EXTRA_REG(0x4135, 0xffff, 0x18),
2691 SNBEP_CBO_EVENT_EXTRA_REG(0x4435, 0xffff, 0x8),
2692 SNBEP_CBO_EVENT_EXTRA_REG(0x4835, 0xffff, 0x8),
2693 SNBEP_CBO_EVENT_EXTRA_REG(0x5035, 0xffff, 0x8),
2694 SNBEP_CBO_EVENT_EXTRA_REG(0x4335, 0xffff, 0x18),
2695 SNBEP_CBO_EVENT_EXTRA_REG(0x4a35, 0xffff, 0x8),
2696 SNBEP_CBO_EVENT_EXTRA_REG(0x2335, 0xffff, 0x10),
2697 SNBEP_CBO_EVENT_EXTRA_REG(0x8335, 0xffff, 0x10),
2698 SNBEP_CBO_EVENT_EXTRA_REG(0x2135, 0xffff, 0x10),
2699 SNBEP_CBO_EVENT_EXTRA_REG(0x8135, 0xffff, 0x10),
2700 SNBEP_CBO_EVENT_EXTRA_REG(0x0136, 0xffff, 0x10),
2701 SNBEP_CBO_EVENT_EXTRA_REG(0x0336, 0xffff, 0x10),
2702 SNBEP_CBO_EVENT_EXTRA_REG(0x4136, 0xffff, 0x18),
2703 SNBEP_CBO_EVENT_EXTRA_REG(0x4436, 0xffff, 0x8),
2704 SNBEP_CBO_EVENT_EXTRA_REG(0x4836, 0xffff, 0x8),
2705 SNBEP_CBO_EVENT_EXTRA_REG(0x4336, 0xffff, 0x18),
2706 SNBEP_CBO_EVENT_EXTRA_REG(0x4a36, 0xffff, 0x8),
2707 SNBEP_CBO_EVENT_EXTRA_REG(0x2336, 0xffff, 0x10),
2708 SNBEP_CBO_EVENT_EXTRA_REG(0x8336, 0xffff, 0x10),
2709 SNBEP_CBO_EVENT_EXTRA_REG(0x2136, 0xffff, 0x10),
2710 SNBEP_CBO_EVENT_EXTRA_REG(0x8136, 0xffff, 0x10),
2711 SNBEP_CBO_EVENT_EXTRA_REG(0x5036, 0xffff, 0x8),
2717 u64 mask = 0; in hswep_cbox_filter_mask()
2718 if (fields & 0x1) in hswep_cbox_filter_mask()
2720 if (fields & 0x2) in hswep_cbox_filter_mask()
2722 if (fields & 0x4) in hswep_cbox_filter_mask()
2724 if (fields & 0x8) in hswep_cbox_filter_mask()
2726 if (fields & 0x10) { in hswep_cbox_filter_mask()
2745 int idx = 0; in hswep_cbox_hw_config()
2759 return 0; in hswep_cbox_hw_config()
2769 u64 filter = uncore_shared_reg_config(box, 0); in hswep_cbox_enable_event()
2770 wrmsrl(reg1->reg, filter & 0xffffffff); in hswep_cbox_enable_event()
2814 u64 flags = 0; in hswep_uncore_sbox_msr_init_box()
2864 if (ev_sel >= 0xb && ev_sel <= 0xe) { in hswep_pcu_hw_config()
2866 reg1->idx = ev_sel - 0xb; in hswep_pcu_hw_config()
2867 reg1->config = event->attr.config1 & (0xff << reg1->idx); in hswep_pcu_hw_config()
2869 return 0; in hswep_pcu_hw_config()
2901 #define HSWEP_PCU_DID 0x2fc0
2902 #define HSWEP_PCU_CAPID4_OFFET 0x94
2903 #define hswep_get_chop(_cap) (((_cap) >> 6) & 0x3)
2942 INTEL_UNCORE_EVENT_DESC(clockticks, "event=0x00,umask=0x00"),
2943 INTEL_UNCORE_EVENT_DESC(cas_count_read, "event=0x04,umask=0x03"),
2946 INTEL_UNCORE_EVENT_DESC(cas_count_write, "event=0x04,umask=0x0c"),
2964 static unsigned hswep_uncore_irp_ctrs[] = {0xa0, 0xa8, 0xb0, 0xb8};
2970 u64 count = 0; in hswep_uncore_irp_read_counter()
3013 UNCORE_EVENT_CONSTRAINT(0x10, 0x3),
3014 UNCORE_EVENT_CONSTRAINT(0x11, 0x3),
3015 UNCORE_EVENT_CONSTRAINT(0x13, 0x1),
3016 UNCORE_EVENT_CONSTRAINT(0x23, 0x1),
3017 UNCORE_EVENT_CONSTRAINT(0x24, 0x1),
3018 UNCORE_EVENT_CONSTRAINT(0x25, 0x1),
3019 UNCORE_EVENT_CONSTRAINT(0x26, 0x3),
3020 UNCORE_EVENT_CONSTRAINT(0x27, 0x1),
3021 UNCORE_EVENT_CONSTRAINT(0x28, 0x3),
3022 UNCORE_EVENT_CONSTRAINT(0x29, 0x3),
3023 UNCORE_EVENT_CONSTRAINT(0x2a, 0x1),
3024 UNCORE_EVENT_CONSTRAINT(0x2b, 0x3),
3025 UNCORE_EVENT_CONSTRAINT(0x2c, 0x3),
3026 UNCORE_EVENT_CONSTRAINT(0x2d, 0x3),
3027 UNCORE_EVENT_CONSTRAINT(0x32, 0x3),
3028 UNCORE_EVENT_CONSTRAINT(0x33, 0x3),
3029 UNCORE_EVENT_CONSTRAINT(0x34, 0x3),
3030 UNCORE_EVENT_CONSTRAINT(0x35, 0x3),
3044 UNCORE_EVENT_CONSTRAINT(0x01, 0x3),
3045 UNCORE_EVENT_CONSTRAINT(0x07, 0x7),
3046 UNCORE_EVENT_CONSTRAINT(0x08, 0x7),
3047 UNCORE_EVENT_CONSTRAINT(0x09, 0x7),
3048 UNCORE_EVENT_CONSTRAINT(0x0a, 0x7),
3049 UNCORE_EVENT_CONSTRAINT(0x0e, 0x7),
3050 UNCORE_EVENT_CONSTRAINT(0x10, 0x3),
3051 UNCORE_EVENT_CONSTRAINT(0x11, 0x3),
3052 UNCORE_EVENT_CONSTRAINT(0x12, 0x3),
3053 UNCORE_EVENT_CONSTRAINT(0x13, 0x1),
3054 UNCORE_EVENT_CONSTRAINT(0x14, 0x3),
3055 UNCORE_EVENT_CONSTRAINT(0x15, 0x3),
3056 UNCORE_EVENT_CONSTRAINT(0x1f, 0x3),
3057 UNCORE_EVENT_CONSTRAINT(0x20, 0x3),
3058 UNCORE_EVENT_CONSTRAINT(0x21, 0x3),
3059 UNCORE_EVENT_CONSTRAINT(0x22, 0x3),
3060 UNCORE_EVENT_CONSTRAINT(0x23, 0x3),
3061 UNCORE_EVENT_CONSTRAINT(0x25, 0x3),
3062 UNCORE_EVENT_CONSTRAINT(0x26, 0x3),
3063 UNCORE_EVENT_CONSTRAINT(0x28, 0x3),
3064 UNCORE_EVENT_CONSTRAINT(0x29, 0x3),
3065 UNCORE_EVENT_CONSTRAINT(0x2c, 0x3),
3066 UNCORE_EVENT_CONSTRAINT(0x2d, 0x3),
3067 UNCORE_EVENT_CONSTRAINT(0x2e, 0x3),
3068 UNCORE_EVENT_CONSTRAINT(0x2f, 0x3),
3069 UNCORE_EVENT_CONSTRAINT(0x31, 0x3),
3070 UNCORE_EVENT_CONSTRAINT(0x32, 0x3),
3071 UNCORE_EVENT_CONSTRAINT(0x33, 0x3),
3072 UNCORE_EVENT_CONSTRAINT(0x34, 0x3),
3073 UNCORE_EVENT_CONSTRAINT(0x36, 0x3),
3074 UNCORE_EVENT_CONSTRAINT(0x37, 0x3),
3075 UNCORE_EVENT_CONSTRAINT(0x38, 0x3),
3076 UNCORE_EVENT_CONSTRAINT(0x39, 0x3),
3109 { /* Home Agent 0 */
3110 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2f30),
3111 .driver_data = UNCORE_PCI_DEV_DATA(HSWEP_PCI_UNCORE_HA, 0),
3114 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2f38),
3117 { /* MC0 Channel 0 */
3118 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2fb0),
3119 .driver_data = UNCORE_PCI_DEV_DATA(HSWEP_PCI_UNCORE_IMC, 0),
3122 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2fb1),
3126 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2fb4),
3130 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2fb5),
3133 { /* MC1 Channel 0 */
3134 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2fd0),
3138 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2fd1),
3142 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2fd4),
3146 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2fd5),
3150 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2f39),
3151 .driver_data = UNCORE_PCI_DEV_DATA(HSWEP_PCI_UNCORE_IRP, 0),
3153 { /* QPI0 Port 0 */
3154 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2f32),
3155 .driver_data = UNCORE_PCI_DEV_DATA(HSWEP_PCI_UNCORE_QPI, 0),
3158 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2f33),
3162 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2f3a),
3166 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2f34),
3167 .driver_data = UNCORE_PCI_DEV_DATA(HSWEP_PCI_UNCORE_R2PCIE, 0),
3169 { /* R3QPI0 Link 0 */
3170 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2f36),
3171 .driver_data = UNCORE_PCI_DEV_DATA(HSWEP_PCI_UNCORE_R3QPI, 0),
3174 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2f37),
3178 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2f3e),
3181 { /* QPI Port 0 filter */
3182 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2f86),
3187 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2f96),
3201 int ret = snbep_pci2phy_map_init(0x2f1e, SNBEP_CPUNODEID, SNBEP_GIDNIDMAP, true); in hswep_uncore_pci_init()
3206 return 0; in hswep_uncore_pci_init()
3229 UNCORE_EVENT_CONSTRAINT(0x09, 0x3),
3230 UNCORE_EVENT_CONSTRAINT(0x11, 0x1),
3231 UNCORE_EVENT_CONSTRAINT(0x36, 0x1),
3232 UNCORE_EVENT_CONSTRAINT(0x3e, 0x1),
3276 /* Bit 7 'Use Occupancy' is not available for counter 0 on BDX */
3278 EVENT_CONSTRAINT(0x80, 0xe, 0x80),
3282 #define BDX_PCU_DID 0x6fc0
3343 UNCORE_EVENT_CONSTRAINT(0x10, 0x3),
3344 UNCORE_EVENT_CONSTRAINT(0x11, 0x3),
3345 UNCORE_EVENT_CONSTRAINT(0x13, 0x1),
3346 UNCORE_EVENT_CONSTRAINT(0x23, 0x1),
3347 UNCORE_EVENT_CONSTRAINT(0x25, 0x1),
3348 UNCORE_EVENT_CONSTRAINT(0x26, 0x3),
3349 UNCORE_EVENT_CONSTRAINT(0x28, 0x3),
3350 UNCORE_EVENT_CONSTRAINT(0x2c, 0x3),
3351 UNCORE_EVENT_CONSTRAINT(0x2d, 0x3),
3365 UNCORE_EVENT_CONSTRAINT(0x01, 0x7),
3366 UNCORE_EVENT_CONSTRAINT(0x07, 0x7),
3367 UNCORE_EVENT_CONSTRAINT(0x08, 0x7),
3368 UNCORE_EVENT_CONSTRAINT(0x09, 0x7),
3369 UNCORE_EVENT_CONSTRAINT(0x0a, 0x7),
3370 UNCORE_EVENT_CONSTRAINT(0x0e, 0x7),
3371 UNCORE_EVENT_CONSTRAINT(0x10, 0x3),
3372 UNCORE_EVENT_CONSTRAINT(0x11, 0x3),
3373 UNCORE_EVENT_CONSTRAINT(0x13, 0x1),
3374 UNCORE_EVENT_CONSTRAINT(0x14, 0x3),
3375 UNCORE_EVENT_CONSTRAINT(0x15, 0x3),
3376 UNCORE_EVENT_CONSTRAINT(0x1f, 0x3),
3377 UNCORE_EVENT_CONSTRAINT(0x20, 0x3),
3378 UNCORE_EVENT_CONSTRAINT(0x21, 0x3),
3379 UNCORE_EVENT_CONSTRAINT(0x22, 0x3),
3380 UNCORE_EVENT_CONSTRAINT(0x23, 0x3),
3381 UNCORE_EVENT_CONSTRAINT(0x25, 0x3),
3382 UNCORE_EVENT_CONSTRAINT(0x26, 0x3),
3383 UNCORE_EVENT_CONSTRAINT(0x28, 0x3),
3384 UNCORE_EVENT_CONSTRAINT(0x29, 0x3),
3385 UNCORE_EVENT_CONSTRAINT(0x2c, 0x3),
3386 UNCORE_EVENT_CONSTRAINT(0x2d, 0x3),
3387 UNCORE_EVENT_CONSTRAINT(0x2e, 0x3),
3388 UNCORE_EVENT_CONSTRAINT(0x2f, 0x3),
3389 UNCORE_EVENT_CONSTRAINT(0x33, 0x3),
3390 UNCORE_EVENT_CONSTRAINT(0x34, 0x3),
3391 UNCORE_EVENT_CONSTRAINT(0x36, 0x3),
3392 UNCORE_EVENT_CONSTRAINT(0x37, 0x3),
3393 UNCORE_EVENT_CONSTRAINT(0x38, 0x3),
3394 UNCORE_EVENT_CONSTRAINT(0x39, 0x3),
3427 { /* Home Agent 0 */
3428 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x6f30),
3429 .driver_data = UNCORE_PCI_DEV_DATA(BDX_PCI_UNCORE_HA, 0),
3432 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x6f38),
3435 { /* MC0 Channel 0 */
3436 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x6fb0),
3437 .driver_data = UNCORE_PCI_DEV_DATA(BDX_PCI_UNCORE_IMC, 0),
3440 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x6fb1),
3444 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x6fb4),
3448 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x6fb5),
3451 { /* MC1 Channel 0 */
3452 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x6fd0),
3456 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x6fd1),
3460 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x6fd4),
3464 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x6fd5),
3468 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x6f39),
3469 .driver_data = UNCORE_PCI_DEV_DATA(BDX_PCI_UNCORE_IRP, 0),
3471 { /* QPI0 Port 0 */
3472 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x6f32),
3473 .driver_data = UNCORE_PCI_DEV_DATA(BDX_PCI_UNCORE_QPI, 0),
3476 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x6f33),
3480 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x6f3a),
3484 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x6f34),
3485 .driver_data = UNCORE_PCI_DEV_DATA(BDX_PCI_UNCORE_R2PCIE, 0),
3487 { /* R3QPI0 Link 0 */
3488 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x6f36),
3489 .driver_data = UNCORE_PCI_DEV_DATA(BDX_PCI_UNCORE_R3QPI, 0),
3492 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x6f37),
3496 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x6f3e),
3499 { /* QPI Port 0 filter */
3500 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x6f86),
3505 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x6f96),
3510 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x6f46),
3524 int ret = snbep_pci2phy_map_init(0x6f1e, SNBEP_CPUNODEID, SNBEP_GIDNIDMAP, true); in bdx_uncore_pci_init()
3530 return 0; in bdx_uncore_pci_init()
3579 UNCORE_EVENT_CONSTRAINT(0x11, 0x1),
3580 UNCORE_EVENT_CONSTRAINT(0x36, 0x1),
3585 SNBEP_CBO_EVENT_EXTRA_REG(0x0334, 0xffff, 0x4),
3586 SNBEP_CBO_EVENT_EXTRA_REG(0x0534, 0xffff, 0x4),
3587 SNBEP_CBO_EVENT_EXTRA_REG(0x0934, 0xffff, 0x4),
3588 SNBEP_CBO_EVENT_EXTRA_REG(0x1134, 0xffff, 0x4),
3589 SNBEP_CBO_EVENT_EXTRA_REG(0x3134, 0xffff, 0x4),
3590 SNBEP_CBO_EVENT_EXTRA_REG(0x9134, 0xffff, 0x4),
3591 SNBEP_CBO_EVENT_EXTRA_REG(0x35, 0xff, 0x8),
3592 SNBEP_CBO_EVENT_EXTRA_REG(0x36, 0xff, 0x8),
3593 SNBEP_CBO_EVENT_EXTRA_REG(0x38, 0xff, 0x3),
3599 u64 mask = 0; in skx_cha_filter_mask()
3601 if (fields & 0x1) in skx_cha_filter_mask()
3603 if (fields & 0x2) in skx_cha_filter_mask()
3605 if (fields & 0x4) in skx_cha_filter_mask()
3607 if (fields & 0x8) { in skx_cha_filter_mask()
3631 int idx = 0; in skx_cha_hw_config()
3648 return 0; in skx_cha_hw_config()
3696 UNCORE_EVENT_CONSTRAINT(0x83, 0x3),
3697 UNCORE_EVENT_CONSTRAINT(0x88, 0xc),
3698 UNCORE_EVENT_CONSTRAINT(0x95, 0xc),
3699 UNCORE_EVENT_CONSTRAINT(0xc0, 0xc),
3700 UNCORE_EVENT_CONSTRAINT(0xc5, 0xc),
3701 UNCORE_EVENT_CONSTRAINT(0xd4, 0xc),
3702 UNCORE_EVENT_CONSTRAINT(0xd5, 0xc),
3727 for (idx = 0; idx < pmu->type->num_boxes; idx++) { in pmu_topology()
3742 return (pmut && !pmut->iio->pci_bus_no && pmu->pmu_idx != zero_bus_pmu) ? 0 : attr->mode; in pmu_iio_mapping_visible()
3748 /* Root bus 0x00 is valid only for pmu_idx = 0. */ in skx_iio_mapping_visible()
3749 return pmu_iio_mapping_visible(kobj, attr, die, 0); in skx_iio_mapping_visible()
3760 return sprintf(buf, "%04x:%02x\n", pmut ? pmut->iio->segment : 0, in skx_iio_mapping_show()
3761 pmut ? pmut->iio->pci_bus_no : 0); in skx_iio_mapping_show()
3774 return 0; in skx_msr_cpu_bus_read()
3779 int res = 0, cpu, current_die; in die_to_cpu()
3819 for (die = 0; die < uncore_max_dies(); die++) { in pmu_alloc_topology()
3823 for (idx = 0; idx < type->num_boxes; idx++) { in pmu_alloc_topology()
3834 return 0; in pmu_alloc_topology()
3836 for (; die >= 0; die--) { in pmu_alloc_topology()
3837 for (idx = 0; idx < type->num_boxes; idx++) in pmu_alloc_topology()
3851 for (die = 0; die < uncore_max_dies(); die++) { in pmu_free_topology()
3852 for (idx = 0; idx < type->num_boxes; idx++) in pmu_free_topology()
3867 for (die = 0; die < uncore_max_dies(); die++) { in skx_pmu_get_topology()
3873 if (ret < 0) in skx_pmu_get_topology()
3890 for (idx = 0; idx < type->num_boxes; idx++) { in skx_iio_topology_cb()
3894 t->iio->pci_bus_no = (cpu_bus_msr >> (idx * BUS_NUM_STRIDE)) & 0xff; in skx_iio_topology_cb()
3897 return 0; in skx_iio_topology_cb()
3919 for (i = 0; groups[i]; i++) { in pmu_clear_mapping_attr()
3941 if (ret < 0) in pmu_set_mapping()
3945 if (ret < 0) in pmu_set_mapping()
3957 for (die = 0; die < uncore_max_dies(); die++) { in pmu_set_mapping()
3973 for (; die >= 0; die--) in pmu_set_mapping()
4037 SKX_IIO_MSR_IOCLK = 0,
4046 [SKX_IIO_MSR_IOCLK] = { 0xa45, 0x1, 0x20, 1, 36 },
4047 [SKX_IIO_MSR_BW] = { 0xb00, 0x1, 0x10, 8, 36 },
4048 [SKX_IIO_MSR_UTIL] = { 0xb08, 0x1, 0x10, 8, 36 },
4053 INTEL_UNCORE_EVENT_DESC(ioclk, "event=0xff,umask=0x10"),
4055 INTEL_UNCORE_EVENT_DESC(bw_in_port0, "event=0xff,umask=0x20"),
4058 INTEL_UNCORE_EVENT_DESC(bw_in_port1, "event=0xff,umask=0x21"),
4061 INTEL_UNCORE_EVENT_DESC(bw_in_port2, "event=0xff,umask=0x22"),
4064 INTEL_UNCORE_EVENT_DESC(bw_in_port3, "event=0xff,umask=0x23"),
4067 INTEL_UNCORE_EVENT_DESC(bw_out_port0, "event=0xff,umask=0x24"),
4070 INTEL_UNCORE_EVENT_DESC(bw_out_port1, "event=0xff,umask=0x25"),
4073 INTEL_UNCORE_EVENT_DESC(bw_out_port2, "event=0xff,umask=0x26"),
4076 INTEL_UNCORE_EVENT_DESC(bw_out_port3, "event=0xff,umask=0x27"),
4080 INTEL_UNCORE_EVENT_DESC(util_in_port0, "event=0xff,umask=0x30"),
4081 INTEL_UNCORE_EVENT_DESC(util_out_port0, "event=0xff,umask=0x31"),
4082 INTEL_UNCORE_EVENT_DESC(util_in_port1, "event=0xff,umask=0x32"),
4083 INTEL_UNCORE_EVENT_DESC(util_out_port1, "event=0xff,umask=0x33"),
4084 INTEL_UNCORE_EVENT_DESC(util_in_port2, "event=0xff,umask=0x34"),
4085 INTEL_UNCORE_EVENT_DESC(util_out_port2, "event=0xff,umask=0x35"),
4086 INTEL_UNCORE_EVENT_DESC(util_in_port3, "event=0xff,umask=0x36"),
4087 INTEL_UNCORE_EVENT_DESC(util_out_port3, "event=0xff,umask=0x37"),
4198 * To determine the number of CHAs, it should read bits 27:0 in the CAPID6
4199 * register which located at Device 30, Function 3, Offset 0x9C. PCI ID 0x2083.
4201 #define SKX_CAPID6 0x9c
4202 #define SKX_CHA_BIT_MASK GENMASK(27, 0)
4207 u32 val = 0; in skx_count_chabox()
4209 dev = pci_get_device(PCI_VENDOR_ID_INTEL, 0x2083, dev); in skx_count_chabox()
4279 return pmu->type->topology[die][pmu->pmu_idx].upi->enabled ? attr->mode : 0; in skx_upi_mapping_visible()
4293 #define SKX_UPI_REG_DID 0x2058
4294 #define SKX_UPI_REGS_ADDR_DEVICE_LINK0 0x0e
4295 #define SKX_UPI_REGS_ADDR_FUNCTION 0x00
4298 * UPI Link Parameter 0
4300 * | 19:16 | 0h | base_nodeid - The NodeID of the sending socket.
4303 #define SKX_KTILP0_OFFSET 0x94
4308 * | 4 | 0h | ll_status_valid — Bit indicates the valid training status
4311 #define SKX_KTIPCSTS_OFFSET 0x120
4334 upi->die_to = (upi_conf >> 16) & 0xf; in upi_fill_topology()
4335 upi->pmu_idx_to = (upi_conf >> 8) & 0x1f; in upi_fill_topology()
4350 for (idx = 0; idx < type->num_boxes; idx++) { in skx_upi_topology_cb()
4449 UNCORE_EVENT_CONSTRAINT(0x23, 0x3),
4468 UNCORE_EVENT_CONSTRAINT(0x1d, 0x1),
4469 UNCORE_EVENT_CONSTRAINT(0x1e, 0x1),
4470 UNCORE_EVENT_CONSTRAINT(0x40, 0x7),
4471 UNCORE_EVENT_CONSTRAINT(0x4e, 0x7),
4472 UNCORE_EVENT_CONSTRAINT(0x4f, 0x7),
4473 UNCORE_EVENT_CONSTRAINT(0x50, 0x7),
4474 UNCORE_EVENT_CONSTRAINT(0x51, 0x7),
4475 UNCORE_EVENT_CONSTRAINT(0x52, 0x7),
4511 { /* MC0 Channel 0 */
4512 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2042),
4513 .driver_data = UNCORE_PCI_DEV_FULL_DATA(10, 2, SKX_PCI_UNCORE_IMC, 0),
4516 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2046),
4520 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x204a),
4523 { /* MC1 Channel 0 */
4524 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2042),
4528 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2046),
4532 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x204a),
4536 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2066),
4537 .driver_data = UNCORE_PCI_DEV_FULL_DATA(8, 0, SKX_PCI_UNCORE_M2M, 0),
4540 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2066),
4541 .driver_data = UNCORE_PCI_DEV_FULL_DATA(9, 0, SKX_PCI_UNCORE_M2M, 1),
4543 { /* UPI0 Link 0 */
4544 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2058),
4545 .driver_data = UNCORE_PCI_DEV_FULL_DATA(14, 0, SKX_PCI_UNCORE_UPI, 0),
4548 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2058),
4549 .driver_data = UNCORE_PCI_DEV_FULL_DATA(15, 0, SKX_PCI_UNCORE_UPI, 1),
4552 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2058),
4553 .driver_data = UNCORE_PCI_DEV_FULL_DATA(16, 0, SKX_PCI_UNCORE_UPI, 2),
4555 { /* M2PCIe 0 */
4556 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2088),
4557 .driver_data = UNCORE_PCI_DEV_FULL_DATA(21, 1, SKX_PCI_UNCORE_M2PCIE, 0),
4560 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2088),
4564 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2088),
4568 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2088),
4571 { /* M3UPI0 Link 0 */
4572 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x204D),
4573 .driver_data = UNCORE_PCI_DEV_FULL_DATA(18, 1, SKX_PCI_UNCORE_M3UPI, 0),
4576 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x204E),
4580 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x204D),
4595 int ret = snbep_pci2phy_map_init(0x2014, SKX_CPUNODEID, SKX_GIDNIDMAP, false); in skx_uncore_pci_init()
4602 return 0; in skx_uncore_pci_init()
4646 reg1->idx = 0; in snr_cha_hw_config()
4648 return 0; in snr_cha_hw_config()
4707 /* Root bus 0x00 is valid only for pmu_idx = 1. */ in snr_iio_mapping_visible()
4735 if (die < 0 || stack_id >= type->num_boxes) { in sad_cfg_iio_topology()
4788 UNCORE_EVENT_CONSTRAINT(0x83, 0x3),
4789 UNCORE_EVENT_CONSTRAINT(0xc0, 0xc),
4790 UNCORE_EVENT_CONSTRAINT(0xd5, 0xc),
4848 if (ev_sel >= 0xb && ev_sel <= 0xe) { in snr_pcu_hw_config()
4850 reg1->idx = ev_sel - 0xb; in snr_pcu_hw_config()
4851 reg1->config = event->attr.config1 & (0xff << reg1->idx); in snr_pcu_hw_config()
4853 return 0; in snr_pcu_hw_config()
4885 [SNR_IIO_MSR_IOCLK] = { 0x1eac, 0x1, 0x10, 1, 48 },
4886 [SNR_IIO_MSR_BW_IN] = { 0x1f00, 0x1, 0x10, 8, 48 },
4891 INTEL_UNCORE_EVENT_DESC(ioclk, "event=0xff,umask=0x10"),
4893 INTEL_UNCORE_EVENT_DESC(bw_in_port0, "event=0xff,umask=0x20"),
4896 INTEL_UNCORE_EVENT_DESC(bw_in_port1, "event=0xff,umask=0x21"),
4899 INTEL_UNCORE_EVENT_DESC(bw_in_port2, "event=0xff,umask=0x22"),
4902 INTEL_UNCORE_EVENT_DESC(bw_in_port3, "event=0xff,umask=0x23"),
4905 INTEL_UNCORE_EVENT_DESC(bw_in_port4, "event=0xff,umask=0x24"),
4908 INTEL_UNCORE_EVENT_DESC(bw_in_port5, "event=0xff,umask=0x25"),
4911 INTEL_UNCORE_EVENT_DESC(bw_in_port6, "event=0xff,umask=0x26"),
4914 INTEL_UNCORE_EVENT_DESC(bw_in_port7, "event=0xff,umask=0x27"),
5038 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x344a),
5039 .driver_data = UNCORE_PCI_DEV_FULL_DATA(12, 0, SNR_PCI_UNCORE_M2M, 0),
5051 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x334a),
5052 .driver_data = UNCORE_PCI_DEV_FULL_DATA(4, 0, SNR_PCI_UNCORE_PCIE3, 0),
5065 int ret = snbep_pci2phy_map_init(0x3460, SKX_CPUNODEID, in snr_uncore_pci_init()
5074 return 0; in snr_uncore_pci_init()
5077 #define SNR_MC_DEVICE_ID 0x3451
5123 return 0; in snr_uncore_mmio_map()
5205 INTEL_UNCORE_EVENT_DESC(clockticks, "event=0x00,umask=0x00"),
5206 INTEL_UNCORE_EVENT_DESC(cas_count_read, "event=0x04,umask=0x0f"),
5209 INTEL_UNCORE_EVENT_DESC(cas_count_write, "event=0x04,umask=0x30"),
5242 [SNR_IMC_DCLK] = { 0x22b0, 0x0, 0, 1, 48 },
5243 [SNR_IMC_DDR] = { 0x2290, 0x8, 0, 2, 48 },
5247 INTEL_UNCORE_EVENT_DESC(dclk, "event=0xff,umask=0x10"),
5249 INTEL_UNCORE_EVENT_DESC(read, "event=0xff,umask=0x20"),
5252 INTEL_UNCORE_EVENT_DESC(write, "event=0xff,umask=0x21"),
5293 0x2a0, 0x2ae, 0x2bc, 0x2ca, 0x2d8, 0x2e6, 0x2f4, 0x302, 0x310,
5294 0x31e, 0x32c, 0x33a, 0x348, 0x356, 0x364, 0x372, 0x380, 0x38e,
5295 0x3aa, 0x3b8, 0x3c6, 0x3d4, 0x3e2, 0x3f0, 0x3fe, 0x40c, 0x41a,
5296 0x428, 0x436, 0x444, 0x452, 0x460, 0x46e, 0x47c, 0x0, 0xe,
5297 0x1c, 0x2a, 0x38, 0x46,
5309 reg1->idx = 0; in icx_cha_hw_config()
5312 return 0; in icx_cha_hw_config()
5341 0x0, 0x20, 0x40, 0x90, 0xb0, 0xd0,
5345 UNCORE_EVENT_CONSTRAINT(0x02, 0x3),
5346 UNCORE_EVENT_CONSTRAINT(0x03, 0x3),
5347 UNCORE_EVENT_CONSTRAINT(0x83, 0x3),
5348 UNCORE_EVENT_CONSTRAINT(0x88, 0xc),
5349 UNCORE_EVENT_CONSTRAINT(0xc0, 0xc),
5350 UNCORE_EVENT_CONSTRAINT(0xc5, 0xc),
5351 UNCORE_EVENT_CONSTRAINT(0xd5, 0xc),
5358 /* Root bus 0x00 is valid only for pmu_idx = 5. */ in icx_iio_mapping_visible()
5447 UNCORE_EVENT_CONSTRAINT(0x14, 0x3),
5448 UNCORE_EVENT_CONSTRAINT(0x23, 0x3),
5449 UNCORE_EVENT_CONSTRAINT(0x2d, 0x3),
5476 0x0, 0x20, 0x40, 0x90, 0xb0, 0xd0,
5480 0x0, 0x10, 0x20, 0x90, 0xa0, 0xb0,
5484 [ICX_IIO_MSR_IOCLK] = { 0xa55, 0x1, 0x20, 1, 48, icx_iio_clk_freerunning_box_offsets },
5485 [ICX_IIO_MSR_BW_IN] = { 0xaa0, 0x1, 0x10, 8, 48, icx_iio_bw_freerunning_box_offsets },
5514 #define ICX_CAPID6 0x9c
5515 #define ICX_CAPID7 0xa0
5520 u64 caps = 0; in icx_count_chabox()
5522 dev = pci_get_device(PCI_VENDOR_ID_INTEL, 0x345b, dev); in icx_count_chabox()
5571 #define ICX_UPI_REGS_ADDR_DEVICE_LINK0 0x02
5572 #define ICX_UPI_REGS_ADDR_FUNCTION 0x01
5595 if (lgc_pkg < 0) { in discover_upi_topology()
5599 for (idx = 0; idx < type->num_boxes; idx++) { in discover_upi_topology()
5661 UNCORE_EVENT_CONSTRAINT(0x1c, 0x1),
5662 UNCORE_EVENT_CONSTRAINT(0x1d, 0x1),
5663 UNCORE_EVENT_CONSTRAINT(0x1e, 0x1),
5664 UNCORE_EVENT_CONSTRAINT(0x1f, 0x1),
5665 UNCORE_EVENT_CONSTRAINT(0x40, 0x7),
5666 UNCORE_EVENT_CONSTRAINT(0x4e, 0x7),
5667 UNCORE_EVENT_CONSTRAINT(0x4f, 0x7),
5668 UNCORE_EVENT_CONSTRAINT(0x50, 0x7),
5700 { /* M2M 0 */
5701 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x344a),
5702 .driver_data = UNCORE_PCI_DEV_FULL_DATA(12, 0, ICX_PCI_UNCORE_M2M, 0),
5705 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x344a),
5706 .driver_data = UNCORE_PCI_DEV_FULL_DATA(13, 0, ICX_PCI_UNCORE_M2M, 1),
5709 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x344a),
5710 .driver_data = UNCORE_PCI_DEV_FULL_DATA(14, 0, ICX_PCI_UNCORE_M2M, 2),
5713 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x344a),
5714 .driver_data = UNCORE_PCI_DEV_FULL_DATA(15, 0, ICX_PCI_UNCORE_M2M, 3),
5716 { /* UPI Link 0 */
5717 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x3441),
5718 .driver_data = UNCORE_PCI_DEV_FULL_DATA(2, 1, ICX_PCI_UNCORE_UPI, 0),
5721 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x3441),
5725 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x3441),
5728 { /* M3UPI Link 0 */
5729 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x3446),
5730 .driver_data = UNCORE_PCI_DEV_FULL_DATA(5, 1, ICX_PCI_UNCORE_M3UPI, 0),
5733 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x3446),
5737 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x3446),
5751 int ret = snbep_pci2phy_map_init(0x3450, SKX_CPUNODEID, in icx_uncore_pci_init()
5759 return 0; in icx_uncore_pci_init()
5811 [ICX_IMC_DCLK] = { 0x22b0, 0x0, 0, 1, 48 },
5812 [ICX_IMC_DDR] = { 0x2290, 0x8, 0, 2, 48 },
5813 [ICX_IMC_DDRT] = { 0x22a0, 0x8, 0, 2, 48 },
5817 INTEL_UNCORE_EVENT_DESC(dclk, "event=0xff,umask=0x10"),
5819 INTEL_UNCORE_EVENT_DESC(read, "event=0xff,umask=0x20"),
5822 INTEL_UNCORE_EVENT_DESC(write, "event=0xff,umask=0x21"),
5826 INTEL_UNCORE_EVENT_DESC(ddrt_read, "event=0xff,umask=0x30"),
5829 INTEL_UNCORE_EVENT_DESC(ddrt_write, "event=0xff,umask=0x31"),
5897 wrmsrl(reg1->reg, 0); in spr_uncore_msr_disable_event()
5899 wrmsrl(hwc->config_base, 0); in spr_uncore_msr_disable_event()
5913 reg1->idx = 0; in spr_cha_hw_config()
5916 return 0; in spr_cha_hw_config()
6013 UNCORE_EVENT_CONSTRAINT(0x14, 0x3),
6014 UNCORE_EVENT_CONSTRAINT(0x2d, 0x3),
6054 INTEL_UNCORE_EVENT_DESC(clockticks, "event=0x01,umask=0x00"),
6055 INTEL_UNCORE_EVENT_DESC(cas_count_read, "event=0x05,umask=0xcf"),
6058 INTEL_UNCORE_EVENT_DESC(cas_count_write, "event=0x05,umask=0xf0"),
6115 #define SPR_UPI_REGS_ADDR_DEVICE_LINK0 0x01
6158 UNCORE_EVENT_CONSTRAINT(0x02, 0x0f),
6159 UNCORE_EVENT_CONSTRAINT(0x05, 0x0f),
6160 UNCORE_EVENT_CONSTRAINT(0x40, 0xf0),
6161 UNCORE_EVENT_CONSTRAINT(0x41, 0xf0),
6162 UNCORE_EVENT_CONSTRAINT(0x42, 0xf0),
6163 UNCORE_EVENT_CONSTRAINT(0x43, 0xf0),
6164 UNCORE_EVENT_CONSTRAINT(0x4b, 0xf0),
6165 UNCORE_EVENT_CONSTRAINT(0x52, 0xf0),
6186 #define UNCORE_SPR_CHA 0
6221 0, 0x8000, 0x10000, 0x18000
6287 [SPR_IIO_MSR_IOCLK] = { 0x340e, 0x1, 0x10, 1, 48 },
6288 [SPR_IIO_MSR_BW_IN] = { 0x3800, 0x1, 0x10, 8, 48 },
6289 [SPR_IIO_MSR_BW_OUT] = { 0x3808, 0x1, 0x10, 8, 48 },
6310 [SPR_IMC_DCLK] = { 0x22b0, 0x0, 0, 1, 48 },
6311 [SPR_IMC_PQ_CYCLES] = { 0x2318, 0x8, 0, 2, 48 },
6315 INTEL_UNCORE_EVENT_DESC(dclk, "event=0xff,umask=0x10"),
6317 INTEL_UNCORE_EVENT_DESC(rpq_cycles, "event=0xff,umask=0x20"),
6318 INTEL_UNCORE_EVENT_DESC(wpq_cycles, "event=0xff,umask=0x21"),
6322 #define SPR_MC_DEVICE_ID 0x3251
6430 for (i = 0; i < num_extra; i++, types++) in uncore_get_uncores()
6453 int max = 0; in uncore_type_max_boxes()
6457 return 0; in uncore_type_max_boxes()
6468 #define SPR_MSR_UNC_CBO_CONFIG 0x2FFE
6499 #define SPR_UNCORE_UPI_PCIID 0x3241
6500 #define SPR_UNCORE_UPI0_DEVFN 0x9
6501 #define SPR_UNCORE_M3UPI_PCIID 0x3246
6502 #define SPR_UNCORE_M3UPI0_DEVFN 0x29
6526 type->num_boxes = 0; in spr_update_device_location()
6534 if (die < 0) in spr_update_device_location()
6573 return 0; in spr_uncore_pci_init()
6578 int ret = snbep_pci2phy_map_init(0x3250, SKX_CPUNODEID, SKX_GIDNIDMAP, true); in spr_uncore_mmio_init()
6581 uncore_mmio_uncores = uncore_get_uncores(UNCORE_ACCESS_MMIO, 0, NULL, in spr_uncore_mmio_init()
6677 [SPR_IIO_MSR_IOCLK] = { 0x290e, 0x01, 0x10, 1, 48 },
6678 [SPR_IIO_MSR_BW_IN] = { 0x360e, 0x10, 0x80, 8, 48 },
6679 [SPR_IIO_MSR_BW_OUT] = { 0x2e0e, 0x10, 0x80, 8, 48 },
6695 uncore_pci_uncores = uncore_get_uncores(UNCORE_ACCESS_PCI, 0, NULL, in gnr_uncore_pci_init()
6698 return 0; in gnr_uncore_pci_init()
6703 uncore_mmio_uncores = uncore_get_uncores(UNCORE_ACCESS_MMIO, 0, NULL, in gnr_uncore_mmio_init()