include/asm/fhc.h

1 /* SPDX-License-Identifier: GPL-2.0 */
11 #define CLOCK_CTRL	0x00UL	/* Main control */
14 #define CLOCK_PWRSTAT	0x30UL	/* Power status */
15 #define CLOCK_PWRPRES	0x40UL	/* Power presence */
18 #define CLOCK_PWRSTAT2	0x70UL	/* Power status two */
30 #define FHC_PREGS_RCS	0x10UL	/* FHC Reset Control/Status Register */
31 #define  FHC_RCS_POR		0x80000000 /* Last reset was a power cycle	*/
32 #define  FHC_RCS_SPOR		0x40000000 /* Last reset was sw power on reset	*/
39 #define FHC_PREGS_CTRL	0x20UL	/* FHC Control Register */
44 #define  FHC_CONTROL_DCD	0x00008000 /* DC-->DC Converter Disable		*/
45 #define  FHC_CONTROL_POFF	0x00004000 /* AC/DC Controller PLL Disable	*/
46 #define  FHC_CONTROL_FOFF	0x00002000 /* FHC Controller PLL Disable	*/
47 #define  FHC_CONTROL_AOFF	0x00001000 /* CPU A SRAM/SBD Low Power Mode	*/
48 #define  FHC_CONTROL_BOFF	0x00000800 /* CPU B SRAM/SBD Low Power Mode	*/
49 #define  FHC_CONTROL_PSOFF	0x00000400 /* Turns off this FHC's power supply	*/
57 #define  FHC_BSR_DA64		0x00040000 /* Port A: 0=128bit 1=64bit data path */
58 #define  FHC_BSR_DB64		0x00020000 /* Port B: 0=128bit 1=64bit data path */
60 #define  FHC_BSR_SA		0x00001c00 /* Port A UPA Speed (from the pins)   */
61 #define  FHC_BSR_SB		0x00000380 /* Port B UPA Speed (from the pins)   */
66 #define FHC_PREGS_ECC	0x40UL	/* FHC ECC Control Register (16 bits) */
67 #define FHC_PREGS_JCTRL	0xf0UL	/* FHC JTAG Control Register */