include/asm/watchdog.h

1 /* SPDX-License-Identifier: GPL-2.0+
3  * include/asm-sh/watchdog.h
15 #define WTCNT_HIGH	0x5a
16 #define WTCSR_HIGH	0xa5
18 #define WTCSR_CKS2	0x04
19 #define WTCSR_CKS1	0x02
20 #define WTCSR_CKS0	0x01
25  * See cpu-sh2/watchdog.h for explanation of this stupidity..
36  * CKS0-2 supports a number of clock division ratios. At the time the watchdog
42  * --------------------------------------------
52 #define WTCSR_CKS_32	0x00
53 #define WTCSR_CKS_64	0x01
54 #define WTCSR_CKS_128	0x02
55 #define WTCSR_CKS_256	0x03
56 #define WTCSR_CKS_512	0x04
57 #define WTCSR_CKS_1024	0x05
58 #define WTCSR_CKS_2048	0x06
59 #define WTCSR_CKS_4096	0x07
63  * 	sh_wdt_read_cnt - Read from Counter
72  *	sh_wdt_write_cnt - Write to Counter
73  *	@val: Value to write
76  *	The upper byte is set manually on each write.
84  *	sh_wdt_write_bst - Write to Counter
85  *	@val: Value to write
88  *	The upper byte is set manually on each write.
95  * 	sh_wdt_read_csr - Read from Control/Status Register
105  * 	sh_wdt_write_csr - Write to Control/Status Register
106  * 	@val: Value to write
109  * 	register. The upper byte is set manually on each write.
117  * 	sh_wdt_read_cnt - Read from Counter
126  *	sh_wdt_write_cnt - Write to Counter
127  *	@val: Value to write
130  *	The upper byte is set manually on each write.
138  * 	sh_wdt_read_csr - Read from Control/Status Register
148  * 	sh_wdt_write_csr - Write to Control/Status Register
149  * 	@val: Value to write
152  * 	register. The upper byte is set manually on each write.