drivers/pci/pci-sh4.h

1 /* SPDX-License-Identifier: GPL-2.0 */
8 #include "pci-sh7780.h"
10 #include "pci-sh7751.h"
15 #define SH4_PCICR		0x100		/* PCI Control Register */
35   #define SH4_PCIINT_MFDE	  0x00000100	/* Master Func. Disable Error */
40   #define SH4_PCIINT_MTABT	  0x00000008	/* Master-Tgt. Abort Error */
41   #define SH4_PCIINT_MMABT	  0x00000004	/* Master-Master Abort Error */
45   #define SH4_PCIINTM_TTADIM	  BIT(14)	/* Target-target abort interrupt */
47   #define SH4_PCIINTM_MDEIM	  BIT(8)	/* Master function disable error */
81   #define SH4_PCIDMABT_RRBN	  0x00000001	/* DMA Arbitor Round-Robin */
85 #define SH4_PCIDCR0		0x18C		/* DMA0 Control Register */
90   #define SH4_PCIDCR_LHLD	  0x00000020	/* Local Address Control */
91   #define SH4_PCIDCR_PHLD	  0x00000010	/* PCI Address Control*/
99 #define SH4_PCIDCR1		0x19C		/* DMA1 Control Register */
103 #define SH4_PCIDCR2		0x1AC		/* DMA2 Control Register */
107 #define SH4_PCIDCR3		0x1BC		/* DMA3 Control Register */
119 #define SH4_PCIPINT		0x1CC		/* Power Mgmnt Int. Register */
122 #define SH4_PCIPINTM		0x1D0		/* Power Mgmnt Mask Register */
131 #define SH4_PCIWCR1		0x1E8		/* Wait Control 1 Register */
132 #define SH4_PCIWCR2		0x1EC		/* Wait Control 2 Register */
133 #define SH4_PCIWCR3		0x1F0		/* Wait Control 3 Register */
135 #define SH4_PCIMCR		0x1F4		/* Memory Control Register */
137 #define SH4_PCIPCTR             0x200		/* Port Control Register */
138   #define SH4_PCIPCTR_P2EN	  0x000400000	/* Port 2 Enable */
139   #define SH4_PCIPCTR_P1EN	  0x000200000	/* Port 1 Enable */
140   #define SH4_PCIPCTR_P0EN	  0x000100000	/* Port 0 Enable */
147 #define SH4_PCIPDTR		0x204		/* Port Data Register */
148   #define SH4_PCIPDTR_PB5	  0x000000020	/* Port 5 Enable */
149   #define SH4_PCIPDTR_PB4	  0x000000010	/* Port 4 Enable */
150   #define SH4_PCIPDTR_PB3	  0x000000008	/* Port 3 Enable */
151   #define SH4_PCIPDTR_PB2	  0x000000004	/* Port 2 Enable */
152   #define SH4_PCIPDTR_PB1	  0x000000002	/* Port 1 Enable */
153   #define SH4_PCIPDTR_PB0	  0x000000001	/* Port 0 Enable */
154 #define SH4_PCIPDR		0x220		/* Port IO Data Register */
156 /* arch/sh/kernel/drivers/pci/ops-sh4.c */
173 	__raw_writel(val, chan->reg_base + reg);  in pci_write_reg()
179 	return __raw_readl(chan->reg_base + reg);  in pci_read_reg()