Lines Matching +full:isa +full:- +full:extensions
1 // SPDX-License-Identifier: GPL-2.0
26 /* Mapping between KVM ISA Extension ID & Host ISA extension ID */
28 /* Single letter extensions (alphabetically sorted) */
37 /* Multi letter extensions (alphabetically sorted) */
125 * The henvcfg.ADUE is read-only zero if menvcfg.ADUE is zero. in kvm_riscv_vcpu_isa_enable_allowed()
141 /* Extensions which don't have any mechanism to disable */ in kvm_riscv_vcpu_isa_disable_allowed()
204 /* Extensions which can be disabled using Smstateen */ in kvm_riscv_vcpu_isa_disable_allowed()
209 * The henvcfg.ADUE is read-only zero if menvcfg.ADUE is zero. in kvm_riscv_vcpu_isa_disable_allowed()
228 set_bit(host_isa, vcpu->arch.isa); in kvm_riscv_vcpu_setup_isa()
236 (unsigned long __user *)(unsigned long)reg->addr; in kvm_riscv_vcpu_get_reg_config()
237 unsigned long reg_num = reg->id & ~(KVM_REG_ARCH_MASK | in kvm_riscv_vcpu_get_reg_config()
242 if (KVM_REG_SIZE(reg->id) != sizeof(unsigned long)) in kvm_riscv_vcpu_get_reg_config()
243 return -EINVAL; in kvm_riscv_vcpu_get_reg_config()
246 case KVM_REG_RISCV_CONFIG_REG(isa): in kvm_riscv_vcpu_get_reg_config()
247 reg_val = vcpu->arch.isa[0] & KVM_RISCV_BASE_ISA_MASK; in kvm_riscv_vcpu_get_reg_config()
250 if (!riscv_isa_extension_available(vcpu->arch.isa, ZICBOM)) in kvm_riscv_vcpu_get_reg_config()
251 return -ENOENT; in kvm_riscv_vcpu_get_reg_config()
255 if (!riscv_isa_extension_available(vcpu->arch.isa, ZICBOZ)) in kvm_riscv_vcpu_get_reg_config()
256 return -ENOENT; in kvm_riscv_vcpu_get_reg_config()
260 reg_val = vcpu->arch.mvendorid; in kvm_riscv_vcpu_get_reg_config()
263 reg_val = vcpu->arch.marchid; in kvm_riscv_vcpu_get_reg_config()
266 reg_val = vcpu->arch.mimpid; in kvm_riscv_vcpu_get_reg_config()
272 return -ENOENT; in kvm_riscv_vcpu_get_reg_config()
275 if (copy_to_user(uaddr, ®_val, KVM_REG_SIZE(reg->id))) in kvm_riscv_vcpu_get_reg_config()
276 return -EFAULT; in kvm_riscv_vcpu_get_reg_config()
285 (unsigned long __user *)(unsigned long)reg->addr; in kvm_riscv_vcpu_set_reg_config()
286 unsigned long reg_num = reg->id & ~(KVM_REG_ARCH_MASK | in kvm_riscv_vcpu_set_reg_config()
291 if (KVM_REG_SIZE(reg->id) != sizeof(unsigned long)) in kvm_riscv_vcpu_set_reg_config()
292 return -EINVAL; in kvm_riscv_vcpu_set_reg_config()
294 if (copy_from_user(®_val, uaddr, KVM_REG_SIZE(reg->id))) in kvm_riscv_vcpu_set_reg_config()
295 return -EFAULT; in kvm_riscv_vcpu_set_reg_config()
298 case KVM_REG_RISCV_CONFIG_REG(isa): in kvm_riscv_vcpu_set_reg_config()
301 * single letter extensions. in kvm_riscv_vcpu_set_reg_config()
304 return -EINVAL; in kvm_riscv_vcpu_set_reg_config()
310 if (reg_val == (vcpu->arch.isa[0] & KVM_RISCV_BASE_ISA_MASK)) in kvm_riscv_vcpu_set_reg_config()
313 if (!vcpu->arch.ran_atleast_once) { in kvm_riscv_vcpu_set_reg_config()
314 /* Ignore the enable/disable request for certain extensions */ in kvm_riscv_vcpu_set_reg_config()
329 /* Do not modify anything beyond single letter extensions */ in kvm_riscv_vcpu_set_reg_config()
330 reg_val = (vcpu->arch.isa[0] & ~KVM_RISCV_BASE_ISA_MASK) | in kvm_riscv_vcpu_set_reg_config()
332 vcpu->arch.isa[0] = reg_val; in kvm_riscv_vcpu_set_reg_config()
335 return -EBUSY; in kvm_riscv_vcpu_set_reg_config()
339 if (!riscv_isa_extension_available(vcpu->arch.isa, ZICBOM)) in kvm_riscv_vcpu_set_reg_config()
340 return -ENOENT; in kvm_riscv_vcpu_set_reg_config()
342 return -EINVAL; in kvm_riscv_vcpu_set_reg_config()
345 if (!riscv_isa_extension_available(vcpu->arch.isa, ZICBOZ)) in kvm_riscv_vcpu_set_reg_config()
346 return -ENOENT; in kvm_riscv_vcpu_set_reg_config()
348 return -EINVAL; in kvm_riscv_vcpu_set_reg_config()
351 if (reg_val == vcpu->arch.mvendorid) in kvm_riscv_vcpu_set_reg_config()
353 if (!vcpu->arch.ran_atleast_once) in kvm_riscv_vcpu_set_reg_config()
354 vcpu->arch.mvendorid = reg_val; in kvm_riscv_vcpu_set_reg_config()
356 return -EBUSY; in kvm_riscv_vcpu_set_reg_config()
359 if (reg_val == vcpu->arch.marchid) in kvm_riscv_vcpu_set_reg_config()
361 if (!vcpu->arch.ran_atleast_once) in kvm_riscv_vcpu_set_reg_config()
362 vcpu->arch.marchid = reg_val; in kvm_riscv_vcpu_set_reg_config()
364 return -EBUSY; in kvm_riscv_vcpu_set_reg_config()
367 if (reg_val == vcpu->arch.mimpid) in kvm_riscv_vcpu_set_reg_config()
369 if (!vcpu->arch.ran_atleast_once) in kvm_riscv_vcpu_set_reg_config()
370 vcpu->arch.mimpid = reg_val; in kvm_riscv_vcpu_set_reg_config()
372 return -EBUSY; in kvm_riscv_vcpu_set_reg_config()
376 return -EINVAL; in kvm_riscv_vcpu_set_reg_config()
379 return -ENOENT; in kvm_riscv_vcpu_set_reg_config()
388 struct kvm_cpu_context *cntx = &vcpu->arch.guest_context; in kvm_riscv_vcpu_get_reg_core()
390 (unsigned long __user *)(unsigned long)reg->addr; in kvm_riscv_vcpu_get_reg_core()
391 unsigned long reg_num = reg->id & ~(KVM_REG_ARCH_MASK | in kvm_riscv_vcpu_get_reg_core()
396 if (KVM_REG_SIZE(reg->id) != sizeof(unsigned long)) in kvm_riscv_vcpu_get_reg_core()
397 return -EINVAL; in kvm_riscv_vcpu_get_reg_core()
399 return -ENOENT; in kvm_riscv_vcpu_get_reg_core()
402 reg_val = cntx->sepc; in kvm_riscv_vcpu_get_reg_core()
407 reg_val = (cntx->sstatus & SR_SPP) ? in kvm_riscv_vcpu_get_reg_core()
410 return -ENOENT; in kvm_riscv_vcpu_get_reg_core()
412 if (copy_to_user(uaddr, ®_val, KVM_REG_SIZE(reg->id))) in kvm_riscv_vcpu_get_reg_core()
413 return -EFAULT; in kvm_riscv_vcpu_get_reg_core()
421 struct kvm_cpu_context *cntx = &vcpu->arch.guest_context; in kvm_riscv_vcpu_set_reg_core()
423 (unsigned long __user *)(unsigned long)reg->addr; in kvm_riscv_vcpu_set_reg_core()
424 unsigned long reg_num = reg->id & ~(KVM_REG_ARCH_MASK | in kvm_riscv_vcpu_set_reg_core()
429 if (KVM_REG_SIZE(reg->id) != sizeof(unsigned long)) in kvm_riscv_vcpu_set_reg_core()
430 return -EINVAL; in kvm_riscv_vcpu_set_reg_core()
432 return -ENOENT; in kvm_riscv_vcpu_set_reg_core()
434 if (copy_from_user(®_val, uaddr, KVM_REG_SIZE(reg->id))) in kvm_riscv_vcpu_set_reg_core()
435 return -EFAULT; in kvm_riscv_vcpu_set_reg_core()
438 cntx->sepc = reg_val; in kvm_riscv_vcpu_set_reg_core()
444 cntx->sstatus |= SR_SPP; in kvm_riscv_vcpu_set_reg_core()
446 cntx->sstatus &= ~SR_SPP; in kvm_riscv_vcpu_set_reg_core()
448 return -ENOENT; in kvm_riscv_vcpu_set_reg_core()
457 struct kvm_vcpu_csr *csr = &vcpu->arch.guest_csr; in kvm_riscv_vcpu_general_get_csr()
460 return -ENOENT; in kvm_riscv_vcpu_general_get_csr()
464 *out_val = (csr->hvip >> VSIP_TO_HVIP_SHIFT) & VSIP_VALID_MASK; in kvm_riscv_vcpu_general_get_csr()
465 *out_val |= csr->hvip & ~IRQ_LOCAL_MASK; in kvm_riscv_vcpu_general_get_csr()
476 struct kvm_vcpu_csr *csr = &vcpu->arch.guest_csr; in kvm_riscv_vcpu_general_set_csr()
479 return -ENOENT; in kvm_riscv_vcpu_general_set_csr()
489 WRITE_ONCE(vcpu->arch.irqs_pending_mask[0], 0); in kvm_riscv_vcpu_general_set_csr()
498 struct kvm_vcpu_smstateen_csr *csr = &vcpu->arch.smstateen_csr; in kvm_riscv_vcpu_smstateen_set_csr()
502 return -EINVAL; in kvm_riscv_vcpu_smstateen_set_csr()
512 struct kvm_vcpu_smstateen_csr *csr = &vcpu->arch.smstateen_csr; in kvm_riscv_vcpu_smstateen_get_csr()
516 return -EINVAL; in kvm_riscv_vcpu_smstateen_get_csr()
527 (unsigned long __user *)(unsigned long)reg->addr; in kvm_riscv_vcpu_get_reg_csr()
528 unsigned long reg_num = reg->id & ~(KVM_REG_ARCH_MASK | in kvm_riscv_vcpu_get_reg_csr()
533 if (KVM_REG_SIZE(reg->id) != sizeof(unsigned long)) in kvm_riscv_vcpu_get_reg_csr()
534 return -EINVAL; in kvm_riscv_vcpu_get_reg_csr()
546 rc = -EINVAL; in kvm_riscv_vcpu_get_reg_csr()
552 rc = -ENOENT; in kvm_riscv_vcpu_get_reg_csr()
558 if (copy_to_user(uaddr, ®_val, KVM_REG_SIZE(reg->id))) in kvm_riscv_vcpu_get_reg_csr()
559 return -EFAULT; in kvm_riscv_vcpu_get_reg_csr()
569 (unsigned long __user *)(unsigned long)reg->addr; in kvm_riscv_vcpu_set_reg_csr()
570 unsigned long reg_num = reg->id & ~(KVM_REG_ARCH_MASK | in kvm_riscv_vcpu_set_reg_csr()
575 if (KVM_REG_SIZE(reg->id) != sizeof(unsigned long)) in kvm_riscv_vcpu_set_reg_csr()
576 return -EINVAL; in kvm_riscv_vcpu_set_reg_csr()
578 if (copy_from_user(®_val, uaddr, KVM_REG_SIZE(reg->id))) in kvm_riscv_vcpu_set_reg_csr()
579 return -EFAULT; in kvm_riscv_vcpu_set_reg_csr()
591 rc = -EINVAL; in kvm_riscv_vcpu_set_reg_csr()
597 rc = -ENOENT; in kvm_riscv_vcpu_set_reg_csr()
614 return -ENOENT; in riscv_vcpu_get_isa_ext_single()
618 return -ENOENT; in riscv_vcpu_get_isa_ext_single()
621 if (__riscv_isa_extension_available(vcpu->arch.isa, host_isa_ext)) in riscv_vcpu_get_isa_ext_single()
635 return -ENOENT; in riscv_vcpu_set_isa_ext_single()
639 return -ENOENT; in riscv_vcpu_set_isa_ext_single()
641 if (reg_val == test_bit(host_isa_ext, vcpu->arch.isa)) in riscv_vcpu_set_isa_ext_single()
644 if (!vcpu->arch.ran_atleast_once) { in riscv_vcpu_set_isa_ext_single()
646 * All multi-letter extension and a few single letter in riscv_vcpu_set_isa_ext_single()
651 set_bit(host_isa_ext, vcpu->arch.isa); in riscv_vcpu_set_isa_ext_single()
654 clear_bit(host_isa_ext, vcpu->arch.isa); in riscv_vcpu_set_isa_ext_single()
656 return -EINVAL; in riscv_vcpu_set_isa_ext_single()
659 return -EBUSY; in riscv_vcpu_set_isa_ext_single()
672 return -ENOENT; in riscv_vcpu_get_isa_ext_multi()
695 return -ENOENT; in riscv_vcpu_set_isa_ext_multi()
713 (unsigned long __user *)(unsigned long)reg->addr; in kvm_riscv_vcpu_get_reg_isa_ext()
714 unsigned long reg_num = reg->id & ~(KVM_REG_ARCH_MASK | in kvm_riscv_vcpu_get_reg_isa_ext()
719 if (KVM_REG_SIZE(reg->id) != sizeof(unsigned long)) in kvm_riscv_vcpu_get_reg_isa_ext()
720 return -EINVAL; in kvm_riscv_vcpu_get_reg_isa_ext()
737 rc = -ENOENT; in kvm_riscv_vcpu_get_reg_isa_ext()
742 if (copy_to_user(uaddr, ®_val, KVM_REG_SIZE(reg->id))) in kvm_riscv_vcpu_get_reg_isa_ext()
743 return -EFAULT; in kvm_riscv_vcpu_get_reg_isa_ext()
752 (unsigned long __user *)(unsigned long)reg->addr; in kvm_riscv_vcpu_set_reg_isa_ext()
753 unsigned long reg_num = reg->id & ~(KVM_REG_ARCH_MASK | in kvm_riscv_vcpu_set_reg_isa_ext()
758 if (KVM_REG_SIZE(reg->id) != sizeof(unsigned long)) in kvm_riscv_vcpu_set_reg_isa_ext()
759 return -EINVAL; in kvm_riscv_vcpu_set_reg_isa_ext()
764 if (copy_from_user(®_val, uaddr, KVM_REG_SIZE(reg->id))) in kvm_riscv_vcpu_set_reg_isa_ext()
765 return -EFAULT; in kvm_riscv_vcpu_set_reg_isa_ext()
775 return -ENOENT; in kvm_riscv_vcpu_set_reg_isa_ext()
796 !riscv_isa_extension_available(vcpu->arch.isa, ZICBOM)) in copy_config_reg_indices()
799 !riscv_isa_extension_available(vcpu->arch.isa, ZICBOZ)) in copy_config_reg_indices()
807 return -EFAULT; in copy_config_reg_indices()
838 return -EFAULT; in copy_core_reg_indices()
850 if (riscv_isa_extension_available(vcpu->arch.isa, SSAIA)) in num_csr_regs()
852 if (riscv_isa_extension_available(vcpu->arch.isa, SMSTATEEN)) in num_csr_regs()
873 return -EFAULT; in copy_csr_reg_indices()
879 if (riscv_isa_extension_available(vcpu->arch.isa, SSAIA)) { in copy_csr_reg_indices()
890 return -EFAULT; in copy_csr_reg_indices()
897 if (riscv_isa_extension_available(vcpu->arch.isa, SMSTATEEN)) { in copy_csr_reg_indices()
908 return -EFAULT; in copy_csr_reg_indices()
932 return -EFAULT; in copy_timer_reg_indices()
942 const struct kvm_cpu_context *cntx = &vcpu->arch.guest_context; in num_fp_f_regs()
944 if (riscv_isa_extension_available(vcpu->arch.isa, f)) in num_fp_f_regs()
945 return sizeof(cntx->fp.f) / sizeof(u32); in num_fp_f_regs()
961 return -EFAULT; in copy_fp_f_reg_indices()
971 const struct kvm_cpu_context *cntx = &vcpu->arch.guest_context; in num_fp_d_regs()
973 if (riscv_isa_extension_available(vcpu->arch.isa, d)) in num_fp_d_regs()
974 return sizeof(cntx->fp.d.f) / sizeof(u64) + 1; in num_fp_d_regs()
987 for (i = 0; i < n-1; i++) { in copy_fp_d_reg_indices()
993 return -EFAULT; in copy_fp_d_reg_indices()
1002 return -EFAULT; in copy_fp_d_reg_indices()
1026 return -EFAULT; in copy_isa_ext_reg_indices()
1056 return -EFAULT; in copy_sbi_ext_reg_indices()
1073 struct kvm_vcpu_sbi_context *scontext = &vcpu->arch.sbi_context; in copy_sbi_reg_indices()
1076 if (scontext->ext_status[KVM_RISCV_SBI_EXT_STA] == KVM_RISCV_SBI_EXT_STATUS_ENABLED) { in copy_sbi_reg_indices()
1087 return -EFAULT; in copy_sbi_reg_indices()
1105 if (!riscv_isa_extension_available(vcpu->arch.isa, v)) in num_vector_regs()
1115 const struct kvm_cpu_context *cntx = &vcpu->arch.guest_context; in copy_vector_reg_indices()
1130 return -EFAULT; in copy_vector_reg_indices()
1136 size = __builtin_ctzl(cntx->vector.vlenb); in copy_vector_reg_indices()
1144 return -EFAULT; in copy_vector_reg_indices()
1153 * kvm_riscv_vcpu_num_regs - how many registers do we present via KVM_GET/SET_ONE_REG
1176 * kvm_riscv_vcpu_copy_reg_indices - get indices of all registers.
1239 switch (reg->id & KVM_REG_RISCV_TYPE_MASK) { in kvm_riscv_vcpu_set_reg()
1266 return -ENOENT; in kvm_riscv_vcpu_set_reg()
1272 switch (reg->id & KVM_REG_RISCV_TYPE_MASK) { in kvm_riscv_vcpu_get_reg()
1299 return -ENOENT; in kvm_riscv_vcpu_get_reg()