Lines Matching +full:reg +full:- +full:names
1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
5 fabric_clk3: fabric-clk3 {
6 compatible = "fixed-clock";
7 #clock-cells = <0>;
8 clock-frequency = <62500000>;
11 fabric_clk1: fabric-clk1 {
12 compatible = "fixed-clock";
13 #clock-cells = <0>;
14 clock-frequency = <125000000>;
18 compatible = "microchip,pcie-host-1.0";
19 #address-cells = <0x3>;
20 #interrupt-cells = <0x1>;
21 #size-cells = <0x2>;
23 reg = <0x20 0x0 0x0 0x8000000>, <0x0 0x43008000 0x0 0x2000>,
25 reg-names = "cfg", "bridge", "ctrl";
26 bus-range = <0x0 0x7f>;
27 interrupt-parent = <&plic>;
29 interrupt-map = <0 0 0 1 &pcie_intc 0>,
33 interrupt-map-mask = <0 0 0 7>;
35 clock-names = "fic0", "fic3";
37 msi-parent = <&pcie>;
38 msi-controller;
40 pcie_intc: interrupt-controller {
41 #address-cells = <0>;
42 #interrupt-cells = <1>;
43 interrupt-controller;