Lines Matching +full:freeze +full:- +full:bridge +full:- +full:controller
1 // SPDX-License-Identifier: GPL-2.0-or-later
29 #include <asm/pci-bridge.h>
32 #include <asm/ppc-pci.h>
38 #include <asm/pnv-pci.h>
64 if (pe->flags & PNV_IODA_PE_DEV) in pe_level_printk()
65 strscpy(pfix, dev_name(&pe->pdev->dev), sizeof(pfix)); in pe_level_printk()
66 else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)) in pe_level_printk()
68 pci_domain_nr(pe->pbus), pe->pbus->number); in pe_level_printk()
70 else if (pe->flags & PNV_IODA_PE_VF) in pe_level_printk()
72 pci_domain_nr(pe->parent_dev->bus), in pe_level_printk()
73 (pe->rid & 0xff00) >> 8, in pe_level_printk()
74 PCI_SLOT(pe->rid), PCI_FUNC(pe->rid)); in pe_level_printk()
78 level, pfix, pe->pe_number, &vaf); in pe_level_printk()
89 return -EINVAL; in iommu_setup()
118 phb->ioda.pe_array[pe_no].phb = phb; in pnv_ioda_init_pe()
119 phb->ioda.pe_array[pe_no].pe_number = pe_no; in pnv_ioda_init_pe()
120 phb->ioda.pe_array[pe_no].dma_setup_done = false; in pnv_ioda_init_pe()
127 rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no, in pnv_ioda_init_pe()
130 pr_warn("%s: Error %lld unfreezing PHB#%x-PE#%x\n", in pnv_ioda_init_pe()
131 __func__, rc, phb->hose->global_number, pe_no); in pnv_ioda_init_pe()
133 return &phb->ioda.pe_array[pe_no]; in pnv_ioda_init_pe()
138 if (!(pe_no >= 0 && pe_no < phb->ioda.total_pe_num)) { in pnv_ioda_reserve_pe()
140 __func__, pe_no, phb->hose->global_number); in pnv_ioda_reserve_pe()
144 mutex_lock(&phb->ioda.pe_alloc_mutex); in pnv_ioda_reserve_pe()
145 if (test_and_set_bit(pe_no, phb->ioda.pe_alloc)) in pnv_ioda_reserve_pe()
147 __func__, pe_no, phb->hose->global_number); in pnv_ioda_reserve_pe()
148 mutex_unlock(&phb->ioda.pe_alloc_mutex); in pnv_ioda_reserve_pe()
158 mutex_lock(&phb->ioda.pe_alloc_mutex); in pnv_ioda_alloc_pe()
161 for (pe = phb->ioda.total_pe_num - 1; pe >= 0; pe--) { in pnv_ioda_alloc_pe()
162 if (test_bit(pe, phb->ioda.pe_alloc)) { in pnv_ioda_alloc_pe()
175 set_bit(i, phb->ioda.pe_alloc); in pnv_ioda_alloc_pe()
178 ret = &phb->ioda.pe_array[pe]; in pnv_ioda_alloc_pe()
181 mutex_unlock(&phb->ioda.pe_alloc_mutex); in pnv_ioda_alloc_pe()
187 struct pnv_phb *phb = pe->phb; in pnv_ioda_free_pe()
188 unsigned int pe_num = pe->pe_number; in pnv_ioda_free_pe()
190 WARN_ON(pe->pdev); in pnv_ioda_free_pe()
193 mutex_lock(&phb->ioda.pe_alloc_mutex); in pnv_ioda_free_pe()
194 clear_bit(pe_num, phb->ioda.pe_alloc); in pnv_ioda_free_pe()
195 mutex_unlock(&phb->ioda.pe_alloc_mutex); in pnv_ioda_free_pe()
206 rc = opal_pci_set_phb_mem_window(phb->opal_id, in pnv_ioda2_init_m64()
208 phb->ioda.m64_bar_idx, in pnv_ioda2_init_m64()
209 phb->ioda.m64_base, in pnv_ioda2_init_m64()
211 phb->ioda.m64_size); in pnv_ioda2_init_m64()
218 rc = opal_pci_phb_mmio_enable(phb->opal_id, in pnv_ioda2_init_m64()
220 phb->ioda.m64_bar_idx, in pnv_ioda2_init_m64()
231 r = &phb->hose->mem_resources[1]; in pnv_ioda2_init_m64()
232 if (phb->ioda.reserved_pe_idx == 0) in pnv_ioda2_init_m64()
233 r->start += (2 * phb->ioda.m64_segsize); in pnv_ioda2_init_m64()
234 else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1)) in pnv_ioda2_init_m64()
235 r->end -= (2 * phb->ioda.m64_segsize); in pnv_ioda2_init_m64()
238 phb->ioda.reserved_pe_idx); in pnv_ioda2_init_m64()
244 rc, desc, phb->ioda.m64_bar_idx); in pnv_ioda2_init_m64()
245 opal_pci_phb_mmio_enable(phb->opal_id, in pnv_ioda2_init_m64()
247 phb->ioda.m64_bar_idx, in pnv_ioda2_init_m64()
249 return -EIO; in pnv_ioda2_init_m64()
255 struct pnv_phb *phb = pci_bus_to_pnvhb(pdev->bus); in pnv_ioda_reserve_dev_m64_pe()
260 base = phb->ioda.m64_base; in pnv_ioda_reserve_dev_m64_pe()
261 sgsz = phb->ioda.m64_segsize; in pnv_ioda_reserve_dev_m64_pe()
263 r = &pdev->resource[i]; in pnv_ioda_reserve_dev_m64_pe()
264 if (!r->parent || !pnv_pci_is_m64(phb, r)) in pnv_ioda_reserve_dev_m64_pe()
267 start = ALIGN_DOWN(r->start - base, sgsz); in pnv_ioda_reserve_dev_m64_pe()
268 end = ALIGN(r->end - base, sgsz); in pnv_ioda_reserve_dev_m64_pe()
284 list_for_each_entry(pdev, &bus->devices, bus_list) { in pnv_ioda_reserve_m64_pe()
287 if (all && pdev->subordinate) in pnv_ioda_reserve_m64_pe()
288 pnv_ioda_reserve_m64_pe(pdev->subordinate, in pnv_ioda_reserve_m64_pe()
305 size = ALIGN(phb->ioda.total_pe_num / 8, sizeof(unsigned long)); in pnv_ioda_pick_m64_pe()
321 if (bitmap_empty(pe_alloc, phb->ioda.total_pe_num)) { in pnv_ioda_pick_m64_pe()
331 i = -1; in pnv_ioda_pick_m64_pe()
332 while ((i = find_next_bit(pe_alloc, phb->ioda.total_pe_num, i + 1)) < in pnv_ioda_pick_m64_pe()
333 phb->ioda.total_pe_num) { in pnv_ioda_pick_m64_pe()
334 pe = &phb->ioda.pe_array[i]; in pnv_ioda_pick_m64_pe()
336 phb->ioda.m64_segmap[pe->pe_number] = pe->pe_number; in pnv_ioda_pick_m64_pe()
338 pe->flags |= PNV_IODA_PE_MASTER; in pnv_ioda_pick_m64_pe()
339 INIT_LIST_HEAD(&pe->slaves); in pnv_ioda_pick_m64_pe()
342 pe->flags |= PNV_IODA_PE_SLAVE; in pnv_ioda_pick_m64_pe()
343 pe->master = master_pe; in pnv_ioda_pick_m64_pe()
344 list_add_tail(&pe->list, &master_pe->slaves); in pnv_ioda_pick_m64_pe()
354 struct pci_controller *hose = phb->hose; in pnv_ioda_parse_m64_window()
355 struct device_node *dn = hose->dn; in pnv_ioda_parse_m64_window()
361 if (phb->type != PNV_PHB_IODA2) { in pnv_ioda_parse_m64_window()
371 r = of_get_property(dn, "ibm,opal-m64-window", NULL); in pnv_ioda_parse_m64_window()
373 pr_info(" No <ibm,opal-m64-window> on %pOF\n", in pnv_ioda_parse_m64_window()
380 * covering the whole 64-bits space. We support only one range. in pnv_ioda_parse_m64_window()
382 if (of_property_read_u32_array(dn, "ibm,opal-available-m64-ranges", in pnv_ioda_parse_m64_window()
391 __func__, m64_range[1], phb->hose->global_number); in pnv_ioda_parse_m64_window()
397 __func__, phb->hose->global_number); in pnv_ioda_parse_m64_window()
402 res = &hose->mem_resources[1]; in pnv_ioda_parse_m64_window()
403 res->name = dn->full_name; in pnv_ioda_parse_m64_window()
404 res->start = of_translate_address(dn, r + 2); in pnv_ioda_parse_m64_window()
405 res->end = res->start + of_read_number(r + 4, 2) - 1; in pnv_ioda_parse_m64_window()
406 res->flags = (IORESOURCE_MEM | IORESOURCE_MEM_64 | IORESOURCE_PREFETCH); in pnv_ioda_parse_m64_window()
408 hose->mem_offset[1] = res->start - pci_addr; in pnv_ioda_parse_m64_window()
410 phb->ioda.m64_size = resource_size(res); in pnv_ioda_parse_m64_window()
411 phb->ioda.m64_segsize = phb->ioda.m64_size / phb->ioda.total_pe_num; in pnv_ioda_parse_m64_window()
412 phb->ioda.m64_base = pci_addr; in pnv_ioda_parse_m64_window()
415 pr_info(" MEM 0x%016llx..0x%016llx -> 0x%016llx (M64 #%d..%d)\n", in pnv_ioda_parse_m64_window()
416 res->start, res->end, pci_addr, m64_range[0], in pnv_ioda_parse_m64_window()
417 m64_range[0] + m64_range[1] - 1); in pnv_ioda_parse_m64_window()
420 phb->ioda.m64_bar_alloc = (unsigned long)-1; in pnv_ioda_parse_m64_window()
423 m64_range[1]--; in pnv_ioda_parse_m64_window()
424 phb->ioda.m64_bar_idx = m64_range[0] + m64_range[1]; in pnv_ioda_parse_m64_window()
426 pr_info(" Using M64 #%d as default window\n", phb->ioda.m64_bar_idx); in pnv_ioda_parse_m64_window()
430 clear_bit(i, &phb->ioda.m64_bar_alloc); in pnv_ioda_parse_m64_window()
436 phb->init_m64 = pnv_ioda2_init_m64; in pnv_ioda_parse_m64_window()
441 struct pnv_ioda_pe *pe = &phb->ioda.pe_array[pe_no]; in pnv_ioda_freeze_pe()
446 if (pe->flags & PNV_IODA_PE_SLAVE) { in pnv_ioda_freeze_pe()
447 pe = pe->master; in pnv_ioda_freeze_pe()
448 if (WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER))) in pnv_ioda_freeze_pe()
451 pe_no = pe->pe_number; in pnv_ioda_freeze_pe()
454 /* Freeze master PE */ in pnv_ioda_freeze_pe()
455 rc = opal_pci_eeh_freeze_set(phb->opal_id, in pnv_ioda_freeze_pe()
459 pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n", in pnv_ioda_freeze_pe()
460 __func__, rc, phb->hose->global_number, pe_no); in pnv_ioda_freeze_pe()
464 /* Freeze slave PEs */ in pnv_ioda_freeze_pe()
465 if (!(pe->flags & PNV_IODA_PE_MASTER)) in pnv_ioda_freeze_pe()
468 list_for_each_entry(slave, &pe->slaves, list) { in pnv_ioda_freeze_pe()
469 rc = opal_pci_eeh_freeze_set(phb->opal_id, in pnv_ioda_freeze_pe()
470 slave->pe_number, in pnv_ioda_freeze_pe()
473 pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n", in pnv_ioda_freeze_pe()
474 __func__, rc, phb->hose->global_number, in pnv_ioda_freeze_pe()
475 slave->pe_number); in pnv_ioda_freeze_pe()
485 pe = &phb->ioda.pe_array[pe_no]; in pnv_ioda_unfreeze_pe()
486 if (pe->flags & PNV_IODA_PE_SLAVE) { in pnv_ioda_unfreeze_pe()
487 pe = pe->master; in pnv_ioda_unfreeze_pe()
488 WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER)); in pnv_ioda_unfreeze_pe()
489 pe_no = pe->pe_number; in pnv_ioda_unfreeze_pe()
493 rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no, opt); in pnv_ioda_unfreeze_pe()
495 pr_warn("%s: Failure %lld clear %d on PHB#%x-PE#%x\n", in pnv_ioda_unfreeze_pe()
496 __func__, rc, opt, phb->hose->global_number, pe_no); in pnv_ioda_unfreeze_pe()
497 return -EIO; in pnv_ioda_unfreeze_pe()
500 if (!(pe->flags & PNV_IODA_PE_MASTER)) in pnv_ioda_unfreeze_pe()
504 list_for_each_entry(slave, &pe->slaves, list) { in pnv_ioda_unfreeze_pe()
505 rc = opal_pci_eeh_freeze_clear(phb->opal_id, in pnv_ioda_unfreeze_pe()
506 slave->pe_number, in pnv_ioda_unfreeze_pe()
509 pr_warn("%s: Failure %lld clear %d on PHB#%x-PE#%x\n", in pnv_ioda_unfreeze_pe()
510 __func__, rc, opt, phb->hose->global_number, in pnv_ioda_unfreeze_pe()
511 slave->pe_number); in pnv_ioda_unfreeze_pe()
512 return -EIO; in pnv_ioda_unfreeze_pe()
527 if (pe_no < 0 || pe_no >= phb->ioda.total_pe_num) in pnv_ioda_get_pe_state()
534 pe = &phb->ioda.pe_array[pe_no]; in pnv_ioda_get_pe_state()
535 if (pe->flags & PNV_IODA_PE_SLAVE) { in pnv_ioda_get_pe_state()
536 pe = pe->master; in pnv_ioda_get_pe_state()
537 WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER)); in pnv_ioda_get_pe_state()
538 pe_no = pe->pe_number; in pnv_ioda_get_pe_state()
542 rc = opal_pci_eeh_freeze_status(phb->opal_id, pe_no, in pnv_ioda_get_pe_state()
546 "PHB#%x-PE#%x state\n", in pnv_ioda_get_pe_state()
548 phb->hose->global_number, pe_no); in pnv_ioda_get_pe_state()
553 if (!(pe->flags & PNV_IODA_PE_MASTER)) in pnv_ioda_get_pe_state()
556 list_for_each_entry(slave, &pe->slaves, list) { in pnv_ioda_get_pe_state()
557 rc = opal_pci_eeh_freeze_status(phb->opal_id, in pnv_ioda_get_pe_state()
558 slave->pe_number, in pnv_ioda_get_pe_state()
564 "PHB#%x-PE#%x state\n", in pnv_ioda_get_pe_state()
566 phb->hose->global_number, slave->pe_number); in pnv_ioda_get_pe_state()
583 int pe_number = phb->ioda.pe_rmap[bdfn]; in pnv_pci_bdfn_to_pe()
588 return &phb->ioda.pe_array[pe_number]; in pnv_pci_bdfn_to_pe()
593 struct pnv_phb *phb = pci_bus_to_pnvhb(dev->bus); in pnv_ioda_get_pe()
598 if (pdn->pe_number == IODA_INVALID_PE) in pnv_ioda_get_pe()
600 return &phb->ioda.pe_array[pdn->pe_number]; in pnv_ioda_get_pe()
615 rc = opal_pci_set_peltv(phb->opal_id, parent->pe_number, in pnv_ioda_set_one_peltv()
616 child->pe_number, op); in pnv_ioda_set_one_peltv()
620 return -ENXIO; in pnv_ioda_set_one_peltv()
623 if (!(child->flags & PNV_IODA_PE_MASTER)) in pnv_ioda_set_one_peltv()
627 list_for_each_entry(slave, &child->slaves, list) { in pnv_ioda_set_one_peltv()
628 rc = opal_pci_set_peltv(phb->opal_id, parent->pe_number, in pnv_ioda_set_one_peltv()
629 slave->pe_number, op); in pnv_ioda_set_one_peltv()
633 return -ENXIO; in pnv_ioda_set_one_peltv()
653 opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number, in pnv_ioda_set_peltv()
655 if (pe->flags & PNV_IODA_PE_MASTER) { in pnv_ioda_set_peltv()
656 list_for_each_entry(slave, &pe->slaves, list) in pnv_ioda_set_peltv()
657 opal_pci_eeh_freeze_clear(phb->opal_id, in pnv_ioda_set_peltv()
658 slave->pe_number, in pnv_ioda_set_peltv()
665 * corresponding PELT-V as well. Otherwise, the error in pnv_ioda_set_peltv()
674 if (pe->flags & PNV_IODA_PE_MASTER) { in pnv_ioda_set_peltv()
675 list_for_each_entry(slave, &pe->slaves, list) { in pnv_ioda_set_peltv()
682 if (pe->flags & (PNV_IODA_PE_BUS_ALL | PNV_IODA_PE_BUS)) in pnv_ioda_set_peltv()
683 pdev = pe->pbus->self; in pnv_ioda_set_peltv()
684 else if (pe->flags & PNV_IODA_PE_DEV) in pnv_ioda_set_peltv()
685 pdev = pe->pdev->bus->self; in pnv_ioda_set_peltv()
687 else if (pe->flags & PNV_IODA_PE_VF) in pnv_ioda_set_peltv()
688 pdev = pe->parent_dev; in pnv_ioda_set_peltv()
694 if (pdn && pdn->pe_number != IODA_INVALID_PE) { in pnv_ioda_set_peltv()
695 parent = &phb->ioda.pe_array[pdn->pe_number]; in pnv_ioda_set_peltv()
701 pdev = pdev->bus->self; in pnv_ioda_set_peltv()
716 if (pdn && pdn->pe_number != IODA_INVALID_PE) { in pnv_ioda_unset_peltv()
717 rc = opal_pci_set_peltv(phb->opal_id, pdn->pe_number, in pnv_ioda_unset_peltv()
718 pe->pe_number, in pnv_ioda_unset_peltv()
722 parent = parent->bus->self; in pnv_ioda_unset_peltv()
725 opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number, in pnv_ioda_unset_peltv()
729 rc = opal_pci_set_peltv(phb->opal_id, pe->pe_number, in pnv_ioda_unset_peltv()
730 pe->pe_number, OPAL_REMOVE_PE_FROM_DOMAIN); in pnv_ioda_unset_peltv()
743 if (pe->pbus) { in pnv_ioda_deconfigure_pe()
748 parent = pe->pbus->self; in pnv_ioda_deconfigure_pe()
749 if (pe->flags & PNV_IODA_PE_BUS_ALL) in pnv_ioda_deconfigure_pe()
750 count = resource_size(&pe->pbus->busn_res); in pnv_ioda_deconfigure_pe()
762 dev_err(&pe->pbus->dev, "Number of subordinate buses %d unsupported\n", in pnv_ioda_deconfigure_pe()
767 rid_end = pe->rid + (count << 8); in pnv_ioda_deconfigure_pe()
770 if (pe->flags & PNV_IODA_PE_VF) in pnv_ioda_deconfigure_pe()
771 parent = pe->parent_dev; in pnv_ioda_deconfigure_pe()
774 parent = pe->pdev->bus->self; in pnv_ioda_deconfigure_pe()
778 rid_end = pe->rid + 1; in pnv_ioda_deconfigure_pe()
782 for (rid = pe->rid; rid < rid_end; rid++) in pnv_ioda_deconfigure_pe()
783 phb->ioda.pe_rmap[rid] = IODA_INVALID_PE; in pnv_ioda_deconfigure_pe()
786 * Release from all parents PELT-V. NPUs don't have a PELTV in pnv_ioda_deconfigure_pe()
789 if (phb->type != PNV_PHB_NPU_OCAPI) in pnv_ioda_deconfigure_pe()
792 rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid, in pnv_ioda_deconfigure_pe()
797 pe->pbus = NULL; in pnv_ioda_deconfigure_pe()
798 pe->pdev = NULL; in pnv_ioda_deconfigure_pe()
800 pe->parent_dev = NULL; in pnv_ioda_deconfigure_pe()
812 if (pe->pbus) { in pnv_ioda_configure_pe()
817 if (pe->flags & PNV_IODA_PE_BUS_ALL) in pnv_ioda_configure_pe()
818 count = resource_size(&pe->pbus->busn_res); in pnv_ioda_configure_pe()
830 dev_err(&pe->pbus->dev, "Number of subordinate buses %d unsupported\n", in pnv_ioda_configure_pe()
835 rid_end = pe->rid + (count << 8); in pnv_ioda_configure_pe()
840 rid_end = pe->rid + 1; in pnv_ioda_configure_pe()
845 * corresponding PELT-V as well. Otherwise, the error in pnv_ioda_configure_pe()
849 rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid, in pnv_ioda_configure_pe()
853 return -ENXIO; in pnv_ioda_configure_pe()
860 if (phb->type != PNV_PHB_NPU_OCAPI) in pnv_ioda_configure_pe()
864 for (rid = pe->rid; rid < rid_end; rid++) in pnv_ioda_configure_pe()
865 phb->ioda.pe_rmap[rid] = pe->pe_number; in pnv_ioda_configure_pe()
867 pe->mve_number = 0; in pnv_ioda_configure_pe()
874 struct pnv_phb *phb = pci_bus_to_pnvhb(dev->bus); in pnv_ioda_setup_dev_PE()
883 if (pdn->pe_number != IODA_INVALID_PE) in pnv_ioda_setup_dev_PE()
899 pdn->pe_number = pe->pe_number; in pnv_ioda_setup_dev_PE()
900 pe->flags = PNV_IODA_PE_DEV; in pnv_ioda_setup_dev_PE()
901 pe->pdev = dev; in pnv_ioda_setup_dev_PE()
902 pe->pbus = NULL; in pnv_ioda_setup_dev_PE()
903 pe->mve_number = -1; in pnv_ioda_setup_dev_PE()
904 pe->rid = dev->bus->number << 8 | pdn->devfn; in pnv_ioda_setup_dev_PE()
905 pe->device_count++; in pnv_ioda_setup_dev_PE()
912 pdn->pe_number = IODA_INVALID_PE; in pnv_ioda_setup_dev_PE()
913 pe->pdev = NULL; in pnv_ioda_setup_dev_PE()
918 mutex_lock(&phb->ioda.pe_list_mutex); in pnv_ioda_setup_dev_PE()
919 list_add_tail(&pe->list, &phb->ioda.pe_list); in pnv_ioda_setup_dev_PE()
920 mutex_unlock(&phb->ioda.pe_list_mutex); in pnv_ioda_setup_dev_PE()
928 * orgiriated by PCIe-to-PCI bridge or PLX switch downstream ports.
940 pe_num = phb->ioda.pe_rmap[bus->number << 8]; in pnv_ioda_setup_bus_PE()
942 pe = &phb->ioda.pe_array[pe_num]; in pnv_ioda_setup_bus_PE()
948 pe = &phb->ioda.pe_array[phb->ioda.root_pe_idx]; in pnv_ioda_setup_bus_PE()
960 __func__, pci_domain_nr(bus), bus->number); in pnv_ioda_setup_bus_PE()
964 pe->flags |= (all ? PNV_IODA_PE_BUS_ALL : PNV_IODA_PE_BUS); in pnv_ioda_setup_bus_PE()
965 pe->pbus = bus; in pnv_ioda_setup_bus_PE()
966 pe->pdev = NULL; in pnv_ioda_setup_bus_PE()
967 pe->mve_number = -1; in pnv_ioda_setup_bus_PE()
968 pe->rid = bus->busn_res.start << 8; in pnv_ioda_setup_bus_PE()
972 &bus->busn_res.start, &bus->busn_res.end, in pnv_ioda_setup_bus_PE()
973 pe->pe_number); in pnv_ioda_setup_bus_PE()
976 &bus->busn_res.start, pe->pe_number); in pnv_ioda_setup_bus_PE()
981 pe->pbus = NULL; in pnv_ioda_setup_bus_PE()
986 list_add_tail(&pe->list, &phb->ioda.pe_list); in pnv_ioda_setup_bus_PE()
993 struct pnv_phb *phb = pci_bus_to_pnvhb(pdev->bus); in pnv_pci_ioda_dma_dev_setup()
1000 /* VF PEs should be pre-configured in pnv_pci_sriov_enable() */ in pnv_pci_ioda_dma_dev_setup()
1001 if (WARN_ON(pdev->is_virtfn)) in pnv_pci_ioda_dma_dev_setup()
1004 pnv_pci_configure_bus(pdev->bus); in pnv_pci_ioda_dma_dev_setup()
1006 pci_info(pdev, "Configured PE#%x\n", pe ? pe->pe_number : 0xfffff); in pnv_pci_ioda_dma_dev_setup()
1016 pci_info(pdev, "Added to existing PE#%x\n", pe->pe_number); in pnv_pci_ioda_dma_dev_setup()
1021 * skip allocating a TCE table, etc unless we get a non-bridge device. in pnv_pci_ioda_dma_dev_setup()
1023 if (!pe->dma_setup_done && !pci_is_bridge(pdev)) { in pnv_pci_ioda_dma_dev_setup()
1024 switch (phb->type) { in pnv_pci_ioda_dma_dev_setup()
1030 __func__, phb->hose->global_number, phb->type); in pnv_pci_ioda_dma_dev_setup()
1035 pdn->pe_number = pe->pe_number; in pnv_pci_ioda_dma_dev_setup()
1036 pe->device_count++; in pnv_pci_ioda_dma_dev_setup()
1038 WARN_ON(get_dma_ops(&pdev->dev) != &dma_iommu_ops); in pnv_pci_ioda_dma_dev_setup()
1039 pdev->dev.archdata.dma_offset = pe->tce_bypass_base; in pnv_pci_ioda_dma_dev_setup()
1040 set_iommu_table_base(&pdev->dev, pe->table_group.tables[0]); in pnv_pci_ioda_dma_dev_setup()
1043 if (pe->table_group.group) in pnv_pci_ioda_dma_dev_setup()
1044 iommu_add_device(&pe->table_group, &pdev->dev); in pnv_pci_ioda_dma_dev_setup()
1048 * Reconfigure TVE#0 to be usable as 64-bit DMA space.
1050 * The first 4GB of virtual memory for a PE is reserved for 32-bit accesses.
1054 * result are limited to the 4GB of virtual memory made available to 32-bit
1057 * In order to work around this, reconfigure TVE#0 to be suitable for 64-bit
1059 * by 64-bit DMAs. This should only be used by devices that want more than
1060 * 4GB, and only on PEs that have no 32-bit devices.
1083 table_pages = alloc_pages_node(pe->phb->hose->node, GFP_KERNEL, in pnv_pci_ioda_dma_64bit_bypass()
1099 rc = opal_pci_map_pe_dma_window(pe->phb->opal_id, in pnv_pci_ioda_dma_64bit_bypass()
1100 pe->pe_number, in pnv_pci_ioda_dma_64bit_bypass()
1102 (pe->pe_number << 1) + 0, in pnv_pci_ioda_dma_64bit_bypass()
1108 pe_info(pe, "Using 64-bit DMA iommu bypass (through TVE#0)\n"); in pnv_pci_ioda_dma_64bit_bypass()
1112 pe_err(pe, "Error configuring 64-bit DMA bypass\n"); in pnv_pci_ioda_dma_64bit_bypass()
1113 return -EIO; in pnv_pci_ioda_dma_64bit_bypass()
1119 struct pnv_phb *phb = pci_bus_to_pnvhb(pdev->bus); in pnv_pci_ioda_iommu_bypass_supported()
1123 if (WARN_ON(!pdn || pdn->pe_number == IODA_INVALID_PE)) in pnv_pci_ioda_iommu_bypass_supported()
1126 pe = &phb->ioda.pe_array[pdn->pe_number]; in pnv_pci_ioda_iommu_bypass_supported()
1127 if (pe->tce_bypass_enabled) { in pnv_pci_ioda_iommu_bypass_supported()
1128 u64 top = pe->tce_bypass_base + memblock_end_of_DRAM() - 1; in pnv_pci_ioda_iommu_bypass_supported()
1136 * bypass the 32-bit region and be usable for 64-bit DMAs. in pnv_pci_ioda_iommu_bypass_supported()
1141 /* pe->pdev should be set if it's a single device, pe->pbus if not */ in pnv_pci_ioda_iommu_bypass_supported()
1142 (pe->device_count == 1 || !pe->pbus) && in pnv_pci_ioda_iommu_bypass_supported()
1143 phb->model == PNV_PHB_MODEL_PHB3) { in pnv_pci_ioda_iommu_bypass_supported()
1148 /* 4GB offset bypasses 32-bit space */ in pnv_pci_ioda_iommu_bypass_supported()
1149 pdev->dev.archdata.dma_offset = (1ULL << 32); in pnv_pci_ioda_iommu_bypass_supported()
1158 return phb->regs + 0x210; in pnv_ioda_get_inval_reg()
1176 /* 01xb - invalidate TCEs that match the specified PE# */ in pnv_pci_phb3_tce_invalidate_pe()
1177 __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(pe->phb); in pnv_pci_phb3_tce_invalidate_pe()
1178 unsigned long val = PHB3_TCE_KILL_INVAL_PE | (pe->pe_number & 0xFF); in pnv_pci_phb3_tce_invalidate_pe()
1188 __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(pe->phb); in pnv_pci_phb3_tce_invalidate()
1193 start |= (pe->pe_number & 0xFF); in pnv_pci_phb3_tce_invalidate()
1198 end |= ((index + npages - 1) << shift); in pnv_pci_phb3_tce_invalidate()
1210 struct pnv_phb *phb = pe->phb; in pnv_pci_ioda2_tce_invalidate_pe()
1212 if (phb->model == PNV_PHB_MODEL_PHB3 && phb->regs) in pnv_pci_ioda2_tce_invalidate_pe()
1215 opal_pci_tce_kill(phb->opal_id, OPAL_PCI_TCE_KILL_PE, in pnv_pci_ioda2_tce_invalidate_pe()
1216 pe->pe_number, 0, 0, 0); in pnv_pci_ioda2_tce_invalidate_pe()
1224 list_for_each_entry_lockless(tgl, &tbl->it_group_list, next) { in pnv_pci_ioda2_tce_invalidate()
1225 struct pnv_ioda_pe *pe = container_of(tgl->table_group, in pnv_pci_ioda2_tce_invalidate()
1227 struct pnv_phb *phb = pe->phb; in pnv_pci_ioda2_tce_invalidate()
1228 unsigned int shift = tbl->it_page_shift; in pnv_pci_ioda2_tce_invalidate()
1230 if (phb->model == PNV_PHB_MODEL_PHB3 && phb->regs) in pnv_pci_ioda2_tce_invalidate()
1234 opal_pci_tce_kill(phb->opal_id, in pnv_pci_ioda2_tce_invalidate()
1236 pe->pe_number, 1u << shift, in pnv_pci_ioda2_tce_invalidate()
1280 struct pnv_phb *phb = pe->phb; in pnv_pci_ioda2_set_window()
1282 const unsigned long size = tbl->it_indirect_levels ? in pnv_pci_ioda2_set_window()
1283 tbl->it_level_size : tbl->it_size; in pnv_pci_ioda2_set_window()
1284 const __u64 start_addr = tbl->it_offset << tbl->it_page_shift; in pnv_pci_ioda2_set_window()
1285 const __u64 win_size = tbl->it_size << tbl->it_page_shift; in pnv_pci_ioda2_set_window()
1288 num, start_addr, start_addr + win_size - 1, in pnv_pci_ioda2_set_window()
1293 * shifted by 1 bit for 32-bits DMA space. in pnv_pci_ioda2_set_window()
1295 rc = opal_pci_map_pe_dma_window(phb->opal_id, in pnv_pci_ioda2_set_window()
1296 pe->pe_number, in pnv_pci_ioda2_set_window()
1297 (pe->pe_number << 1) + num, in pnv_pci_ioda2_set_window()
1298 tbl->it_indirect_levels + 1, in pnv_pci_ioda2_set_window()
1299 __pa(tbl->it_base), in pnv_pci_ioda2_set_window()
1307 pnv_pci_link_table_and_group(phb->hose->node, num, in pnv_pci_ioda2_set_window()
1308 tbl, &pe->table_group); in pnv_pci_ioda2_set_window()
1316 uint16_t window_id = (pe->pe_number << 1 ) + 1; in pnv_pci_ioda2_set_bypass()
1319 pe_info(pe, "%sabling 64-bit DMA bypass\n", enable ? "En" : "Dis"); in pnv_pci_ioda2_set_bypass()
1324 rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id, in pnv_pci_ioda2_set_bypass()
1325 pe->pe_number, in pnv_pci_ioda2_set_bypass()
1327 pe->tce_bypass_base, in pnv_pci_ioda2_set_bypass()
1330 rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id, in pnv_pci_ioda2_set_bypass()
1331 pe->pe_number, in pnv_pci_ioda2_set_bypass()
1333 pe->tce_bypass_base, in pnv_pci_ioda2_set_bypass()
1339 pe->tce_bypass_enabled = enable; in pnv_pci_ioda2_set_bypass()
1348 int nid = pe->phb->hose->node; in pnv_pci_ioda2_create_table()
1349 __u64 bus_offset = num ? pe->tce_bypass_base : table_group->tce32_start; in pnv_pci_ioda2_create_table()
1355 return -ENOMEM; in pnv_pci_ioda2_create_table()
1357 tbl->it_ops = &pnv_ioda2_iommu_ops; in pnv_pci_ioda2_create_table()
1395 * end up being multilevel and with on-demand allocation in place, in pnv_pci_ioda2_setup_default_config()
1410 * order to save memory by relying on on-demain TCE level allocation. in pnv_pci_ioda2_setup_default_config()
1414 rc = pnv_pci_ioda2_create_table(&pe->table_group, 0, PAGE_SHIFT, in pnv_pci_ioda2_setup_default_config()
1417 pe_err(pe, "Failed to create 32-bit TCE table, err %ld", in pnv_pci_ioda2_setup_default_config()
1425 if (window_size > pe->phb->ioda.m32_pci_base) { in pnv_pci_ioda2_setup_default_config()
1426 res_start = pe->phb->ioda.m32_pci_base >> tbl->it_page_shift; in pnv_pci_ioda2_setup_default_config()
1427 res_end = min(window_size, SZ_4G) >> tbl->it_page_shift; in pnv_pci_ioda2_setup_default_config()
1430 tbl->it_index = (pe->phb->hose->global_number << 16) | pe->pe_number; in pnv_pci_ioda2_setup_default_config()
1431 if (iommu_init_table(tbl, pe->phb->hose->node, res_start, res_end)) in pnv_pci_ioda2_setup_default_config()
1432 rc = pnv_pci_ioda2_set_window(&pe->table_group, 0, tbl); in pnv_pci_ioda2_setup_default_config()
1434 rc = -ENOMEM; in pnv_pci_ioda2_setup_default_config()
1436 pe_err(pe, "Failed to configure 32-bit TCE table, err %ld\n", rc); in pnv_pci_ioda2_setup_default_config()
1448 if (pe->pdev) in pnv_pci_ioda2_setup_default_config()
1449 set_iommu_table_base(&pe->pdev->dev, tbl); in pnv_pci_ioda2_setup_default_config()
1459 struct pnv_phb *phb = pe->phb; in pnv_pci_ioda2_unset_window()
1464 ret = opal_pci_map_pe_dma_window(phb->opal_id, pe->pe_number, in pnv_pci_ioda2_unset_window()
1465 (pe->pe_number << 1) + num, in pnv_pci_ioda2_unset_window()
1473 pnv_pci_unlink_table_and_group(table_group->tables[num], table_group); in pnv_pci_ioda2_unset_window()
1484 unsigned entries_shift = window_shift - page_shift; in pnv_pci_ioda2_get_table_size()
1494 entries_shift = (entries_shift + levels - 1) / levels; in pnv_pci_ioda2_get_table_size()
1499 for ( ; levels; --levels) { in pnv_pci_ioda2_get_table_size()
1520 (*ptbl)->it_allocated_size = pnv_pci_ioda2_get_table_size( in pnv_pci_ioda2_create_table_userspace()
1529 list_for_each_entry(dev, &bus->devices, bus_list) { in pnv_ioda_setup_bus_dma()
1530 set_iommu_table_base(&dev->dev, pe->table_group.tables[0]); in pnv_ioda_setup_bus_dma()
1531 dev->dev.archdata.dma_offset = pe->tce_bypass_base; in pnv_ioda_setup_bus_dma()
1533 if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate) in pnv_ioda_setup_bus_dma()
1534 pnv_ioda_setup_bus_dma(pe, dev->subordinate); in pnv_ioda_setup_bus_dma()
1544 struct iommu_table *tbl = pe->table_group.tables[0]; in pnv_ioda2_take_ownership()
1554 pnv_pci_ioda2_unset_window(&pe->table_group, 0); in pnv_ioda2_take_ownership()
1555 if (pe->pbus) in pnv_ioda2_take_ownership()
1556 pnv_ioda_setup_bus_dma(pe, pe->pbus); in pnv_ioda2_take_ownership()
1557 else if (pe->pdev) in pnv_ioda2_take_ownership()
1558 set_iommu_table_base(&pe->pdev->dev, NULL); in pnv_ioda2_take_ownership()
1571 if (pe->table_group.tables[0]) in pnv_ioda2_release_ownership()
1574 if (pe->pbus) in pnv_ioda2_release_ownership()
1575 pnv_ioda_setup_bus_dma(pe, pe->pbus); in pnv_ioda2_release_ownership()
1594 pe->tce_bypass_base = 1ull << 59; in pnv_pci_ioda2_setup_dma_pe()
1596 /* The PE will reserve all possible 32-bits space */ in pnv_pci_ioda2_setup_dma_pe()
1597 pe_info(pe, "Setting up 32-bit TCE table at 0..%08x\n", in pnv_pci_ioda2_setup_dma_pe()
1598 phb->ioda.m32_pci_base); in pnv_pci_ioda2_setup_dma_pe()
1601 pe->table_group.tce32_start = 0; in pnv_pci_ioda2_setup_dma_pe()
1602 pe->table_group.tce32_size = phb->ioda.m32_pci_base; in pnv_pci_ioda2_setup_dma_pe()
1603 pe->table_group.max_dynamic_windows_supported = in pnv_pci_ioda2_setup_dma_pe()
1605 pe->table_group.max_levels = POWERNV_IOMMU_MAX_LEVELS; in pnv_pci_ioda2_setup_dma_pe()
1606 pe->table_group.pgsizes = pnv_ioda_parse_tce_sizes(phb); in pnv_pci_ioda2_setup_dma_pe()
1613 pe->table_group.ops = &pnv_pci_ioda2_ops; in pnv_pci_ioda2_setup_dma_pe()
1614 iommu_register_group(&pe->table_group, phb->hose->global_number, in pnv_pci_ioda2_setup_dma_pe()
1615 pe->pe_number); in pnv_pci_ioda2_setup_dma_pe()
1617 pe->dma_setup_done = true; in pnv_pci_ioda2_setup_dma_pe()
1624 * The IRQ data is mapped in the PCI-MSI domain and the EOI OPAL call
1626 * numbers of the in-the-middle MSI domain are vector numbers and it's
1631 struct pci_controller *hose = irq_data_get_irq_chip_data(d->parent_data); in pnv_opal_pci_msi_eoi()
1632 struct pnv_phb *phb = hose->private_data; in pnv_opal_pci_msi_eoi()
1634 return opal_pci_msi_eoi(phb->opal_id, d->parent_data->hwirq); in pnv_opal_pci_msi_eoi()
1657 dev_dbg(&dev->dev, "%s: setup %s-bit MSI for vector #%d\n", __func__, in __pnv_pci_ioda_msi_setup()
1662 return -ENXIO; in __pnv_pci_ioda_msi_setup()
1665 if (pe->mve_number < 0) in __pnv_pci_ioda_msi_setup()
1666 return -ENXIO; in __pnv_pci_ioda_msi_setup()
1668 /* Force 32-bit MSI on some broken devices */ in __pnv_pci_ioda_msi_setup()
1669 if (dev->no_64bit_msi) in __pnv_pci_ioda_msi_setup()
1673 rc = opal_pci_set_xive_pe(phb->opal_id, pe->pe_number, xive_num); in __pnv_pci_ioda_msi_setup()
1677 return -EIO; in __pnv_pci_ioda_msi_setup()
1683 rc = opal_get_msi_64(phb->opal_id, pe->mve_number, xive_num, 1, in __pnv_pci_ioda_msi_setup()
1686 pr_warn("%s: OPAL error %d getting 64-bit MSI data\n", in __pnv_pci_ioda_msi_setup()
1688 return -EIO; in __pnv_pci_ioda_msi_setup()
1690 msg->address_hi = be64_to_cpu(addr64) >> 32; in __pnv_pci_ioda_msi_setup()
1691 msg->address_lo = be64_to_cpu(addr64) & 0xfffffffful; in __pnv_pci_ioda_msi_setup()
1695 rc = opal_get_msi_32(phb->opal_id, pe->mve_number, xive_num, 1, in __pnv_pci_ioda_msi_setup()
1698 pr_warn("%s: OPAL error %d getting 32-bit MSI data\n", in __pnv_pci_ioda_msi_setup()
1700 return -EIO; in __pnv_pci_ioda_msi_setup()
1702 msg->address_hi = 0; in __pnv_pci_ioda_msi_setup()
1703 msg->address_lo = be32_to_cpu(addr32); in __pnv_pci_ioda_msi_setup()
1705 msg->data = be32_to_cpu(data); in __pnv_pci_ioda_msi_setup()
1713 * controller.
1729 d = d->parent_data; in pnv_msi_shutdown()
1730 if (d->chip->irq_shutdown) in pnv_msi_shutdown()
1731 d->chip->irq_shutdown(d); in pnv_msi_shutdown()
1747 .name = "PNV-PCI-MSI",
1766 struct pnv_phb *phb = hose->private_data; in pnv_msi_compose_msg()
1769 rc = __pnv_pci_ioda_msi_setup(phb, pdev, d->hwirq, in pnv_msi_compose_msg()
1770 entry->pci.msi_attrib.is_64, msg); in pnv_msi_compose_msg()
1772 dev_err(&pdev->dev, "Failed to setup %s-bit MSI #%ld : %d\n", in pnv_msi_compose_msg()
1773 entry->pci.msi_attrib.is_64 ? "64" : "32", d->hwirq, rc); in pnv_msi_compose_msg()
1783 struct pnv_phb *phb = hose->private_data; in pnv_msi_eoi()
1785 if (phb->model == PNV_PHB_MODEL_PHB3) { in pnv_msi_eoi()
1791 WARN_ON_ONCE(opal_pci_msi_eoi(phb->opal_id, d->hwirq)); in pnv_msi_eoi()
1798 .name = "PNV-MSI",
1813 parent_fwspec.fwnode = domain->parent->fwnode; in pnv_irq_parent_domain_alloc()
1828 struct pci_controller *hose = domain->host_data; in pnv_irq_domain_alloc()
1829 struct pnv_phb *phb = hose->private_data; in pnv_irq_domain_alloc()
1831 struct pci_dev *pdev = msi_desc_to_pci_dev(info->desc); in pnv_irq_domain_alloc()
1835 hwirq = msi_bitmap_alloc_hwirqs(&phb->msi_bmp, nr_irqs); in pnv_irq_domain_alloc()
1837 dev_warn(&pdev->dev, "failed to find a free MSI\n"); in pnv_irq_domain_alloc()
1838 return -ENOSPC; in pnv_irq_domain_alloc()
1841 dev_dbg(&pdev->dev, "%s bridge %pOF %d/%x #%d\n", __func__, in pnv_irq_domain_alloc()
1842 hose->dn, virq, hwirq, nr_irqs); in pnv_irq_domain_alloc()
1846 phb->msi_base + hwirq + i); in pnv_irq_domain_alloc()
1857 irq_domain_free_irqs_parent(domain, virq, i - 1); in pnv_irq_domain_alloc()
1858 msi_bitmap_free_hwirqs(&phb->msi_bmp, hwirq, nr_irqs); in pnv_irq_domain_alloc()
1867 struct pnv_phb *phb = hose->private_data; in pnv_irq_domain_free()
1869 pr_debug("%s bridge %pOF %d/%lx #%d\n", __func__, hose->dn, in pnv_irq_domain_free()
1870 virq, d->hwirq, nr_irqs); in pnv_irq_domain_free()
1872 msi_bitmap_free_hwirqs(&phb->msi_bmp, d->hwirq, nr_irqs); in pnv_irq_domain_free()
1873 /* XIVE domain is cleared through ->msi_free() */ in pnv_irq_domain_free()
1883 struct pnv_phb *phb = hose->private_data; in pnv_msi_allocate_domains()
1886 hose->fwnode = irq_domain_alloc_named_id_fwnode("PNV-MSI", phb->opal_id); in pnv_msi_allocate_domains()
1887 if (!hose->fwnode) in pnv_msi_allocate_domains()
1888 return -ENOMEM; in pnv_msi_allocate_domains()
1890 hose->dev_domain = irq_domain_create_hierarchy(parent, 0, count, in pnv_msi_allocate_domains()
1891 hose->fwnode, in pnv_msi_allocate_domains()
1893 if (!hose->dev_domain) { in pnv_msi_allocate_domains()
1894 pr_err("PCI: failed to create IRQ domain bridge %pOF (domain %d)\n", in pnv_msi_allocate_domains()
1895 hose->dn, hose->global_number); in pnv_msi_allocate_domains()
1896 irq_domain_free_fwnode(hose->fwnode); in pnv_msi_allocate_domains()
1897 return -ENOMEM; in pnv_msi_allocate_domains()
1900 hose->msi_domain = pci_msi_create_irq_domain(of_node_to_fwnode(hose->dn), in pnv_msi_allocate_domains()
1902 hose->dev_domain); in pnv_msi_allocate_domains()
1903 if (!hose->msi_domain) { in pnv_msi_allocate_domains()
1904 pr_err("PCI: failed to create MSI IRQ domain bridge %pOF (domain %d)\n", in pnv_msi_allocate_domains()
1905 hose->dn, hose->global_number); in pnv_msi_allocate_domains()
1906 irq_domain_free_fwnode(hose->fwnode); in pnv_msi_allocate_domains()
1907 irq_domain_remove(hose->dev_domain); in pnv_msi_allocate_domains()
1908 return -ENOMEM; in pnv_msi_allocate_domains()
1917 const __be32 *prop = of_get_property(phb->hose->dn, in pnv_pci_init_ioda_msis()
1918 "ibm,opal-msi-ranges", NULL); in pnv_pci_init_ioda_msis()
1921 prop = of_get_property(phb->hose->dn, "msi-ranges", NULL); in pnv_pci_init_ioda_msis()
1926 phb->msi_base = be32_to_cpup(prop); in pnv_pci_init_ioda_msis()
1928 if (msi_bitmap_alloc(&phb->msi_bmp, count, phb->hose->dn)) { in pnv_pci_init_ioda_msis()
1930 phb->hose->global_number); in pnv_pci_init_ioda_msis()
1935 count, phb->msi_base); in pnv_pci_init_ioda_msis()
1937 pnv_msi_allocate_domains(phb->hose, count); in pnv_pci_init_ioda_msis()
1943 struct pnv_phb *phb = pe->phb; in pnv_ioda_setup_pe_res()
1948 if (!res || !res->flags || res->start > res->end || in pnv_ioda_setup_pe_res()
1949 res->flags & IORESOURCE_UNSET) in pnv_ioda_setup_pe_res()
1952 if (res->flags & IORESOURCE_IO) { in pnv_ioda_setup_pe_res()
1953 region.start = res->start - phb->ioda.io_pci_base; in pnv_ioda_setup_pe_res()
1954 region.end = res->end - phb->ioda.io_pci_base; in pnv_ioda_setup_pe_res()
1955 index = region.start / phb->ioda.io_segsize; in pnv_ioda_setup_pe_res()
1957 while (index < phb->ioda.total_pe_num && in pnv_ioda_setup_pe_res()
1959 phb->ioda.io_segmap[index] = pe->pe_number; in pnv_ioda_setup_pe_res()
1960 rc = opal_pci_map_pe_mmio_window(phb->opal_id, in pnv_ioda_setup_pe_res()
1961 pe->pe_number, OPAL_IO_WINDOW_TYPE, 0, index); in pnv_ioda_setup_pe_res()
1964 __func__, rc, index, pe->pe_number); in pnv_ioda_setup_pe_res()
1968 region.start += phb->ioda.io_segsize; in pnv_ioda_setup_pe_res()
1971 } else if ((res->flags & IORESOURCE_MEM) && in pnv_ioda_setup_pe_res()
1973 region.start = res->start - in pnv_ioda_setup_pe_res()
1974 phb->hose->mem_offset[0] - in pnv_ioda_setup_pe_res()
1975 phb->ioda.m32_pci_base; in pnv_ioda_setup_pe_res()
1976 region.end = res->end - in pnv_ioda_setup_pe_res()
1977 phb->hose->mem_offset[0] - in pnv_ioda_setup_pe_res()
1978 phb->ioda.m32_pci_base; in pnv_ioda_setup_pe_res()
1979 index = region.start / phb->ioda.m32_segsize; in pnv_ioda_setup_pe_res()
1981 while (index < phb->ioda.total_pe_num && in pnv_ioda_setup_pe_res()
1983 phb->ioda.m32_segmap[index] = pe->pe_number; in pnv_ioda_setup_pe_res()
1984 rc = opal_pci_map_pe_mmio_window(phb->opal_id, in pnv_ioda_setup_pe_res()
1985 pe->pe_number, OPAL_M32_WINDOW_TYPE, 0, index); in pnv_ioda_setup_pe_res()
1988 __func__, rc, index, pe->pe_number); in pnv_ioda_setup_pe_res()
1992 region.start += phb->ioda.m32_segsize; in pnv_ioda_setup_pe_res()
2013 BUG_ON(!(pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))); in pnv_ioda_setup_pe_seg()
2015 list_for_each_entry(pdev, &pe->pbus->devices, bus_list) { in pnv_ioda_setup_pe_seg()
2017 pnv_ioda_setup_pe_res(pe, &pdev->resource[i]); in pnv_ioda_setup_pe_seg()
2024 if (!(pe->flags & PNV_IODA_PE_BUS_ALL) || !pci_is_bridge(pdev)) in pnv_ioda_setup_pe_seg()
2028 &pdev->resource[PCI_BRIDGE_RESOURCES + i]); in pnv_ioda_setup_pe_seg()
2039 ret = opal_pci_get_phb_diag_data2(phb->opal_id, phb->diag_data, in pnv_pci_diag_data_set()
2040 phb->diag_data_size); in pnv_pci_diag_data_set()
2042 return -EIO; in pnv_pci_diag_data_set()
2045 pnv_pci_dump_phb_diag_data(phb->hose, phb->diag_data); in pnv_pci_diag_data_set()
2057 for (pe_num = 0; pe_num < phb->ioda.total_pe_num; pe_num++) { in pnv_pci_ioda_pe_dump()
2058 struct pnv_ioda_pe *pe = &phb->ioda.pe_array[pe_num]; in pnv_pci_ioda_pe_dump()
2060 if (!test_bit(pe_num, phb->ioda.pe_alloc)) in pnv_pci_ioda_pe_dump()
2064 pe->rid, pe->device_count, in pnv_pci_ioda_pe_dump()
2065 (pe->flags & PNV_IODA_PE_DEV) ? "dev " : "", in pnv_pci_ioda_pe_dump()
2066 (pe->flags & PNV_IODA_PE_BUS) ? "bus " : "", in pnv_pci_ioda_pe_dump()
2067 (pe->flags & PNV_IODA_PE_BUS_ALL) ? "all " : "", in pnv_pci_ioda_pe_dump()
2068 (pe->flags & PNV_IODA_PE_MASTER) ? "master " : "", in pnv_pci_ioda_pe_dump()
2069 (pe->flags & PNV_IODA_PE_SLAVE) ? "slave " : "", in pnv_pci_ioda_pe_dump()
2070 (pe->flags & PNV_IODA_PE_VF) ? "vf " : ""); in pnv_pci_ioda_pe_dump()
2089 phb = hose->private_data; in pnv_pci_ioda_create_dbgfs()
2091 sprintf(name, "PCI%04x", hose->global_number); in pnv_pci_ioda_create_dbgfs()
2092 phb->dbgfs = debugfs_create_dir(name, arch_debugfs_dir); in pnv_pci_ioda_create_dbgfs()
2094 debugfs_create_file_unsafe("dump_diag_regs", 0200, phb->dbgfs, in pnv_pci_ioda_create_dbgfs()
2096 debugfs_create_file_unsafe("dump_ioda_pe_state", 0200, phb->dbgfs, in pnv_pci_ioda_create_dbgfs()
2104 struct pci_dev *dev = bus->self; in pnv_pci_enable_bridge()
2108 if (list_empty(&bus->devices)) in pnv_pci_enable_bridge()
2112 * If there's a bridge associated with that bus enable it. This works in pnv_pci_enable_bridge()
2120 pci_err(dev, "Error enabling bridge (%d)\n", rc); in pnv_pci_enable_bridge()
2125 list_for_each_entry(child, &bus->children, node) in pnv_pci_enable_bridge()
2134 pnv_pci_enable_bridge(hose->bus); in pnv_pci_enable_bridges()
2156 * create against the parent PCI bridge. For that case, we
2165 struct pci_dev *bridge; in pnv_pci_window_alignment() local
2167 bridge = bus->self; in pnv_pci_window_alignment()
2168 while (bridge) { in pnv_pci_window_alignment()
2169 if (pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE) { in pnv_pci_window_alignment()
2175 bridge = bridge->bus->self; in pnv_pci_window_alignment()
2180 * alignment for any 64-bit resource, PCIe doesn't care and in pnv_pci_window_alignment()
2181 * bridges only do 64-bit prefetchable anyway. in pnv_pci_window_alignment()
2183 if (phb->ioda.m64_segsize && pnv_pci_is_m64_flags(type)) in pnv_pci_window_alignment()
2184 return phb->ioda.m64_segsize; in pnv_pci_window_alignment()
2186 return phb->ioda.m32_segsize; in pnv_pci_window_alignment()
2188 return phb->ioda.io_segsize; in pnv_pci_window_alignment()
2193 * bridge behind the root port with PHB's windows in order
2203 struct pnv_phb *phb = hose->private_data; in pnv_pci_fixup_bridge_resources()
2204 struct pci_dev *bridge = bus->self; in pnv_pci_fixup_bridge_resources() local
2209 /* Check if we need apply fixup to the bridge's windows */ in pnv_pci_fixup_bridge_resources()
2210 if (!pci_is_root_bus(bridge->bus) && in pnv_pci_fixup_bridge_resources()
2211 !pci_is_root_bus(bridge->bus->self->bus)) in pnv_pci_fixup_bridge_resources()
2216 r = &bridge->resource[PCI_BRIDGE_RESOURCES + i]; in pnv_pci_fixup_bridge_resources()
2217 if (!r->flags || !r->parent) in pnv_pci_fixup_bridge_resources()
2221 if (r->flags & type & IORESOURCE_IO) in pnv_pci_fixup_bridge_resources()
2222 w = &hose->io_resource; in pnv_pci_fixup_bridge_resources()
2225 phb->ioda.m64_segsize) in pnv_pci_fixup_bridge_resources()
2226 w = &hose->mem_resources[1]; in pnv_pci_fixup_bridge_resources()
2227 else if (r->flags & type & IORESOURCE_MEM) { in pnv_pci_fixup_bridge_resources()
2228 w = &hose->mem_resources[0]; in pnv_pci_fixup_bridge_resources()
2232 r->start = w->start; in pnv_pci_fixup_bridge_resources()
2233 r->end = w->end; in pnv_pci_fixup_bridge_resources()
2235 /* The 64KB 32-bits MSI region shouldn't be included in in pnv_pci_fixup_bridge_resources()
2236 * the 32-bits bridge window. Otherwise, we can see strange in pnv_pci_fixup_bridge_resources()
2240 * 32-bits bridge window. in pnv_pci_fixup_bridge_resources()
2243 r->end += 0x10000; in pnv_pci_fixup_bridge_resources()
2244 r->end -= 0x100000; in pnv_pci_fixup_bridge_resources()
2251 struct pci_dev *bridge = bus->self; in pnv_pci_configure_bus() local
2253 bool all = (bridge && pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE); in pnv_pci_configure_bus()
2255 dev_info(&bus->dev, "Configuring PE for bus\n"); in pnv_pci_configure_bus()
2258 if (WARN_ON(list_empty(&bus->devices))) in pnv_pci_configure_bus()
2289 if (!pdn || pdn->pe_number == IODA_INVALID_PE) { in pnv_pci_enable_device_hook()
2306 if (pdn->pe_number == IODA_INVALID_PE) { in pnv_ocapi_enable_device_hook()
2316 struct iommu_table *tbl = pe->table_group.tables[0]; in pnv_pci_ioda2_release_pe_dma()
2319 if (!pe->dma_setup_done) in pnv_pci_ioda2_release_pe_dma()
2322 rc = pnv_pci_ioda2_unset_window(&pe->table_group, 0); in pnv_pci_ioda2_release_pe_dma()
2327 if (pe->table_group.group) { in pnv_pci_ioda2_release_pe_dma()
2328 iommu_group_put(pe->table_group.group); in pnv_pci_ioda2_release_pe_dma()
2329 WARN_ON(pe->table_group.group); in pnv_pci_ioda2_release_pe_dma()
2339 struct pnv_phb *phb = pe->phb; in pnv_ioda_free_pe_seg()
2343 for (idx = 0; idx < phb->ioda.total_pe_num; idx++) { in pnv_ioda_free_pe_seg()
2344 if (map[idx] != pe->pe_number) in pnv_ioda_free_pe_seg()
2347 rc = opal_pci_map_pe_mmio_window(phb->opal_id, in pnv_ioda_free_pe_seg()
2348 phb->ioda.reserved_pe_idx, win, 0, idx); in pnv_ioda_free_pe_seg()
2360 struct pnv_phb *phb = pe->phb; in pnv_ioda_release_pe_seg()
2362 if (phb->type == PNV_PHB_IODA2) { in pnv_ioda_release_pe_seg()
2364 phb->ioda.m32_segmap); in pnv_ioda_release_pe_seg()
2370 struct pnv_phb *phb = pe->phb; in pnv_ioda_release_pe()
2375 mutex_lock(&phb->ioda.pe_list_mutex); in pnv_ioda_release_pe()
2376 list_del(&pe->list); in pnv_ioda_release_pe()
2377 mutex_unlock(&phb->ioda.pe_list_mutex); in pnv_ioda_release_pe()
2379 switch (phb->type) { in pnv_ioda_release_pe()
2390 pnv_ioda_deconfigure_pe(pe->phb, pe); in pnv_ioda_release_pe()
2393 if (pe->flags & PNV_IODA_PE_MASTER) { in pnv_ioda_release_pe()
2394 list_for_each_entry_safe(slave, tmp, &pe->slaves, list) { in pnv_ioda_release_pe()
2395 list_del(&slave->list); in pnv_ioda_release_pe()
2406 if (phb->ioda.root_pe_idx == pe->pe_number) in pnv_ioda_release_pe()
2414 struct pnv_phb *phb = pci_bus_to_pnvhb(pdev->bus); in pnv_pci_release_device()
2419 if (pdev->is_virtfn) in pnv_pci_release_device()
2422 if (!pdn || pdn->pe_number == IODA_INVALID_PE) in pnv_pci_release_device()
2431 if (pdev->is_physfn) in pnv_pci_release_device()
2432 kfree(pdev->dev.archdata.iov_data); in pnv_pci_release_device()
2443 pe = &phb->ioda.pe_array[pdn->pe_number]; in pnv_pci_release_device()
2444 pdn->pe_number = IODA_INVALID_PE; in pnv_pci_release_device()
2446 WARN_ON(--pe->device_count < 0); in pnv_pci_release_device()
2447 if (pe->device_count == 0) in pnv_pci_release_device()
2453 struct pnv_phb *phb = hose->private_data; in pnv_pci_ioda_shutdown()
2455 opal_pci_reset(phb->opal_id, OPAL_RESET_PCI_IODA_TABLE, in pnv_pci_ioda_shutdown()
2464 list_for_each_entry(pe, &phb->ioda.pe_list, list) { in pnv_pci_ioda_dma_bus_setup()
2465 if (!(pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))) in pnv_pci_ioda_dma_bus_setup()
2468 if (!pe->pbus) in pnv_pci_ioda_dma_bus_setup()
2471 if (bus->number == ((pe->rid >> 8) & 0xFF)) { in pnv_pci_ioda_dma_bus_setup()
2472 pe->pbus = bus; in pnv_pci_ioda_dma_bus_setup()
2482 struct pnv_phb *phb = hose->private_data; in pnv_pci_device_group()
2486 return ERR_PTR(-ENODEV); in pnv_pci_device_group()
2490 return ERR_PTR(-ENODEV); in pnv_pci_device_group()
2492 if (!pe->table_group.group) in pnv_pci_device_group()
2493 return ERR_PTR(-ENODEV); in pnv_pci_device_group()
2495 return iommu_group_ref_get(pe->table_group.group); in pnv_pci_device_group()
2543 prop64 = of_get_property(np, "ibm,opal-phbid", NULL); in pnv_pci_init_ioda_phb()
2545 pr_err(" Missing \"ibm,opal-phbid\" property !\n"); in pnv_pci_init_ioda_phb()
2549 pr_debug(" PHB-ID : 0x%016llx\n", phb_id); in pnv_pci_init_ioda_phb()
2556 /* Allocate PCI controller */ in pnv_pci_init_ioda_phb()
2557 phb->hose = hose = pcibios_alloc_controller(np); in pnv_pci_init_ioda_phb()
2558 if (!phb->hose) { in pnv_pci_init_ioda_phb()
2559 pr_err(" Can't allocate PCI controller for %pOF\n", in pnv_pci_init_ioda_phb()
2565 spin_lock_init(&phb->lock); in pnv_pci_init_ioda_phb()
2566 prop32 = of_get_property(np, "bus-range", &len); in pnv_pci_init_ioda_phb()
2568 hose->first_busno = be32_to_cpu(prop32[0]); in pnv_pci_init_ioda_phb()
2569 hose->last_busno = be32_to_cpu(prop32[1]); in pnv_pci_init_ioda_phb()
2571 pr_warn(" Broken <bus-range> on %pOF\n", np); in pnv_pci_init_ioda_phb()
2572 hose->first_busno = 0; in pnv_pci_init_ioda_phb()
2573 hose->last_busno = 0xff; in pnv_pci_init_ioda_phb()
2575 hose->private_data = phb; in pnv_pci_init_ioda_phb()
2576 phb->hub_id = hub_id; in pnv_pci_init_ioda_phb()
2577 phb->opal_id = phb_id; in pnv_pci_init_ioda_phb()
2578 phb->type = ioda_type; in pnv_pci_init_ioda_phb()
2579 mutex_init(&phb->ioda.pe_alloc_mutex); in pnv_pci_init_ioda_phb()
2582 if (of_device_is_compatible(np, "ibm,p7ioc-pciex")) in pnv_pci_init_ioda_phb()
2583 phb->model = PNV_PHB_MODEL_P7IOC; in pnv_pci_init_ioda_phb()
2584 else if (of_device_is_compatible(np, "ibm,power8-pciex")) in pnv_pci_init_ioda_phb()
2585 phb->model = PNV_PHB_MODEL_PHB3; in pnv_pci_init_ioda_phb()
2587 phb->model = PNV_PHB_MODEL_UNKNOWN; in pnv_pci_init_ioda_phb()
2590 prop32 = of_get_property(np, "ibm,phb-diag-data-size", NULL); in pnv_pci_init_ioda_phb()
2592 phb->diag_data_size = be32_to_cpup(prop32); in pnv_pci_init_ioda_phb()
2594 phb->diag_data_size = PNV_PCI_DIAG_BUF_SIZE; in pnv_pci_init_ioda_phb()
2596 phb->diag_data = kzalloc(phb->diag_data_size, GFP_KERNEL); in pnv_pci_init_ioda_phb()
2597 if (!phb->diag_data) in pnv_pci_init_ioda_phb()
2599 phb->diag_data_size); in pnv_pci_init_ioda_phb()
2601 /* Parse 32-bit and IO ranges (if any) */ in pnv_pci_init_ioda_phb()
2602 pci_process_bridge_OF_ranges(hose, np, !hose->global_number); in pnv_pci_init_ioda_phb()
2606 phb->regs_phys = r.start; in pnv_pci_init_ioda_phb()
2607 phb->regs = ioremap(r.start, resource_size(&r)); in pnv_pci_init_ioda_phb()
2608 if (phb->regs == NULL) in pnv_pci_init_ioda_phb()
2613 phb->ioda.total_pe_num = 1; in pnv_pci_init_ioda_phb()
2614 prop32 = of_get_property(np, "ibm,opal-num-pes", NULL); in pnv_pci_init_ioda_phb()
2616 phb->ioda.total_pe_num = be32_to_cpup(prop32); in pnv_pci_init_ioda_phb()
2617 prop32 = of_get_property(np, "ibm,opal-reserved-pe", NULL); in pnv_pci_init_ioda_phb()
2619 phb->ioda.reserved_pe_idx = be32_to_cpup(prop32); in pnv_pci_init_ioda_phb()
2622 for (segno = 0; segno < ARRAY_SIZE(phb->ioda.pe_rmap); segno++) in pnv_pci_init_ioda_phb()
2623 phb->ioda.pe_rmap[segno] = IODA_INVALID_PE; in pnv_pci_init_ioda_phb()
2625 /* Parse 64-bit MMIO range */ in pnv_pci_init_ioda_phb()
2628 phb->ioda.m32_size = resource_size(&hose->mem_resources[0]); in pnv_pci_init_ioda_phb()
2630 phb->ioda.m32_size += 0x10000; in pnv_pci_init_ioda_phb()
2632 phb->ioda.m32_segsize = phb->ioda.m32_size / phb->ioda.total_pe_num; in pnv_pci_init_ioda_phb()
2633 phb->ioda.m32_pci_base = hose->mem_resources[0].start - hose->mem_offset[0]; in pnv_pci_init_ioda_phb()
2634 phb->ioda.io_size = hose->pci_io_size; in pnv_pci_init_ioda_phb()
2635 phb->ioda.io_segsize = phb->ioda.io_size / phb->ioda.total_pe_num; in pnv_pci_init_ioda_phb()
2636 phb->ioda.io_pci_base = 0; /* XXX calculate this ? */ in pnv_pci_init_ioda_phb()
2639 size = ALIGN(max_t(unsigned, phb->ioda.total_pe_num, 8) / 8, in pnv_pci_init_ioda_phb()
2642 size += phb->ioda.total_pe_num * sizeof(phb->ioda.m64_segmap[0]); in pnv_pci_init_ioda_phb()
2644 size += phb->ioda.total_pe_num * sizeof(phb->ioda.m32_segmap[0]); in pnv_pci_init_ioda_phb()
2646 size += phb->ioda.total_pe_num * sizeof(struct pnv_ioda_pe); in pnv_pci_init_ioda_phb()
2651 phb->ioda.pe_alloc = aux; in pnv_pci_init_ioda_phb()
2652 phb->ioda.m64_segmap = aux + m64map_off; in pnv_pci_init_ioda_phb()
2653 phb->ioda.m32_segmap = aux + m32map_off; in pnv_pci_init_ioda_phb()
2654 for (segno = 0; segno < phb->ioda.total_pe_num; segno++) { in pnv_pci_init_ioda_phb()
2655 phb->ioda.m64_segmap[segno] = IODA_INVALID_PE; in pnv_pci_init_ioda_phb()
2656 phb->ioda.m32_segmap[segno] = IODA_INVALID_PE; in pnv_pci_init_ioda_phb()
2658 phb->ioda.pe_array = aux + pemap_off; in pnv_pci_init_ioda_phb()
2665 pnv_ioda_reserve_pe(phb, phb->ioda.reserved_pe_idx); in pnv_pci_init_ioda_phb()
2666 if (phb->ioda.reserved_pe_idx == 0) { in pnv_pci_init_ioda_phb()
2667 phb->ioda.root_pe_idx = 1; in pnv_pci_init_ioda_phb()
2668 pnv_ioda_reserve_pe(phb, phb->ioda.root_pe_idx); in pnv_pci_init_ioda_phb()
2669 } else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1)) { in pnv_pci_init_ioda_phb()
2670 phb->ioda.root_pe_idx = phb->ioda.reserved_pe_idx - 1; in pnv_pci_init_ioda_phb()
2671 pnv_ioda_reserve_pe(phb, phb->ioda.root_pe_idx); in pnv_pci_init_ioda_phb()
2675 phb->ioda.root_pe_idx = root_pe->pe_number; in pnv_pci_init_ioda_phb()
2678 INIT_LIST_HEAD(&phb->ioda.pe_list); in pnv_pci_init_ioda_phb()
2679 mutex_init(&phb->ioda.pe_list_mutex); in pnv_pci_init_ioda_phb()
2682 rc = opal_pci_set_phb_mem_window(opal->phb_id, in pnv_pci_init_ioda_phb()
2691 phb->ioda.total_pe_num, phb->ioda.reserved_pe_idx, in pnv_pci_init_ioda_phb()
2692 phb->ioda.m32_size, phb->ioda.m32_segsize); in pnv_pci_init_ioda_phb()
2693 if (phb->ioda.m64_size) in pnv_pci_init_ioda_phb()
2695 phb->ioda.m64_size, phb->ioda.m64_segsize); in pnv_pci_init_ioda_phb()
2696 if (phb->ioda.io_size) in pnv_pci_init_ioda_phb()
2698 phb->ioda.io_size, phb->ioda.io_segsize); in pnv_pci_init_ioda_phb()
2701 phb->hose->ops = &pnv_pci_ops; in pnv_pci_init_ioda_phb()
2702 phb->get_pe_state = pnv_ioda_get_pe_state; in pnv_pci_init_ioda_phb()
2703 phb->freeze_pe = pnv_ioda_freeze_pe; in pnv_pci_init_ioda_phb()
2704 phb->unfreeze_pe = pnv_ioda_unfreeze_pe; in pnv_pci_init_ioda_phb()
2713 * for the P2P bridge bars so that each PCI bus (excluding in pnv_pci_init_ioda_phb()
2718 switch (phb->type) { in pnv_pci_init_ioda_phb()
2720 hose->controller_ops = pnv_npu_ocapi_ioda_controller_ops; in pnv_pci_init_ioda_phb()
2723 hose->controller_ops = pnv_pci_ioda_controller_ops; in pnv_pci_init_ioda_phb()
2759 if (!phb->init_m64 || phb->init_m64(phb)) in pnv_pci_init_ioda_phb()
2760 hose->mem_resources[1].flags = 0; in pnv_pci_init_ioda_phb()
2778 struct pnv_phb *phb = pci_bus_to_pnvhb(dev->bus); in pnv_npu2_opencapi_cfg_size_fixup()
2783 if (phb->type == PNV_PHB_NPU_OCAPI) in pnv_npu2_opencapi_cfg_size_fixup()
2784 dev->cfg_size = PCI_CFG_SPACE_EXP_SIZE; in pnv_npu2_opencapi_cfg_size_fixup()