dts/fsl/t104xrdb.dtsi

4  * Copyright 2014 - 2015 Freescale Semiconductor Inc.
14  *	 names of its contributors may be used to endorse or promote products
42 	reserved-memory {
43 		#address-cells = <2>;
44 		#size-cells = <2>;
47 		bman_fbpr: bman-fbpr {
51 		qman_fqd: qman-fqd {
55 		qman_pfdr: qman-pfdr {
62 		reg = <0xf 0xfe124000 0 0x2000>;
68 			#address-cells = <1>;
69 			#size-cells = <1>;
70 			compatible = "cfi-flash";
71 			reg = <0x0 0x0 0x8000000>;
72 			bank-width = <2>;
73 			device-width = <1>;
77 			#address-cells = <1>;
78 			#size-cells = <1>;
79 			compatible = "fsl,ifc-nand";
80 			reg = <0x2 0x0 0x10000>;
84 			reg = <3 0 0x300>;
96 	bportals: bman-portals@ff4000000 {
100 	qportals: qman-portals@ff6000000 {
106 		reg = <0xf 0xfe000000 0 0x00001000>;
110 				#address-cells = <1>;
111 				#size-cells = <1>;
112 				compatible = "micron,n25q512ax3", "jedec,spi-nor";
113 				reg = <0>;
114 				spi-max-frequency = <10000000>; /* input clock */
118 				reg = <3>;
119 				spi-max-frequency = <2000000>; /* input clock */
126 				reg = <0x4c>;
131 			i2c-mux@77 {
133 				reg = <0x77>;
134 				#address-cells = <1>;
135 				#size-cells = <0>;
141 				phy-handle = <&phy_rgmii_0>;
142 				phy-connection-type = "rgmii-id";
146 				phy-handle = <&phy_rgmii_1>;
147 				phy-connection-type = "rgmii-id";
151 				phy_sgmii_2: ethernet-phy@3 {
152 					reg = <0x03>;
155 				phy_rgmii_0: ethernet-phy@1 {
156 					reg = <0x01>;
159 				phy_rgmii_1: ethernet-phy@2 {
160 					reg = <0x02>;
167 		reg = <0xf 0xfe240000 0 0x10000>;
182 		reg = <0xf 0xfe250000 0 0x10000>;
197 		reg = <0xf 0xfe260000 0 0x10000>;
212 		reg = <0xf 0xfe270000 0 0x10000>;
228 		reg = <0xf 0xfe140000 0 0x480>;
229 		brg-frequency = <0>;
230 		bus-frequency = <0>;
233 			compatible = "fsl,t1040-qe-si";
234 			reg = <0x700 0x80>;
238 			compatible = "fsl,t1040-qe-siram";
239 			reg = <0x1000 0x800>;
243 			compatible = "fsl,ucc-hdlc";
244 			rx-clock-name = "clk8";
245 			tx-clock-name = "clk9";
246 			fsl,rx-sync-clock = "rsync_pin";
247 			fsl,tx-sync-clock = "tsync_pin";
248 			fsl,tx-timeslot-mask = <0xfffffffe>;
249 			fsl,rx-timeslot-mask = <0xfffffffe>;
250 			fsl,tdm-framer-type = "e1";
251 			fsl,tdm-id = <0>;
252 			fsl,siram-entry-id = <0>;
253 			fsl,tdm-interface;
257 			compatible = "fsl,t1040-ucc-uart";
258 			port-number = <0>;
259 			rx-clock-name = "brg2";
260 			tx-clock-name = "brg2";