dts/fsl/p1020rdb-pd.dts

2  * P1020 RDB-PD Device Tree Source (32-bit address map)
14  *       names of its contributors may be used to endorse or promote products
35 /include/ "p1020si-pre.dtsi"
37 	model = "fsl,P1020RDB-PD";
38 	compatible = "fsl,P1020RDB-PD";
45 		reg = <0x0 0xffe05000 0x0 0x1000>;
54 			#address-cells = <1>;
55 			#size-cells = <1>;
56 			compatible = "cfi-flash";
57 			reg = <0x0 0x0 0x4000000>;
58 			bank-width = <2>;
59 			device-width = <1>;
63 				reg = <0x0 0x00020000>;
69 				reg = <0x00020000 0x003e0000>;
75 				reg = <0x00400000 0x03a00000>;
82 				reg = <0x3e00000 0x00100000>;
83 				label = "NOR Vitesse-7385 Firmware";
84 				read-only;
89 				/* 512KB for u-boot Bootloader Image */
90 				/* 512KB for u-boot Environment Variables */
91 				reg = <0x03f00000 0x00100000>;
92 				label = "NOR U-Boot Image";
93 				read-only;
98 			#address-cells = <1>;
99 			#size-cells = <1>;
100 			compatible = "fsl,p1020-fcm-nand",
101 				     "fsl,elbc-fcm-nand";
102 			reg = <0x1 0x0 0x40000>;
106 				/* 1MB for u-boot Bootloader Image */
107 				reg = <0x0 0x00100000>;
108 				label = "NAND U-Boot Image";
109 				read-only;
114 				reg = <0x00100000 0x00100000>;
120 				reg = <0x00200000 0x00400000>;
126 				reg = <0x00600000 0x07a00000>;
132 			compatible = "fsl,p1020rdb-pd-cpld";
133 			reg = <0x2 0x0 0x20000>;
137 			#address-cells = <1>;
138 			#size-cells = <1>;
139 			compatible = "vitesse-7385";
140 			reg = <0x3 0x0 0x20000>;
150 				reg = <0x68>;
156 				#address-cells = <1>;
157 				#size-cells = <1>;
158 				compatible = "spansion,s25sl12801", "jedec,spi-nor";
159 				reg = <0>;
161 				spi-max-frequency = <40000000>;
164 					/* 512KB for u-boot Bootloader Image */
165 					reg = <0x0 0x00080000>;
166 					label = "SPI U-Boot Image";
167 					read-only;
172 					reg = <0x00080000 0x00080000>;
178 					reg = <0x00100000 0x00400000>;
184 					reg = <0x00500000 0x00b00000>;
191 				reg = <1>;
192 				spi-max-frequency = <8000000>;
197 				reg = <2>;
198 				spi-max-frequency = <8000000>;
203 			phy0: ethernet-phy@0 {
205 				reg = <0x0>;
208 			phy1: ethernet-phy@1 {
210 				reg = <0x1>;
215 			tbi1: tbi-phy@11 {
216 				reg = <0x11>;
217 				device_type = "tbi-phy";
222 			tbi2: tbi-phy@11 {
223 				reg = <0x11>;
224 				device_type = "tbi-phy";
229 			compatible = "fsl,etsec-ptp";
230 			reg = <0xb0e00 0xb0>;
232 			fsl,tclk-period	= <10>;
233 			fsl,tmr-prsc	= <2>;
234 			fsl,tmr-add	= <0x80000016>;
235 			fsl,tmr-fiper1	= <999999990>;
236 			fsl,tmr-fiper2	= <99990>;
237 			fsl,max-adj	= <199999999>;
241 			fixed-link = <1 1 1000 0 0>;
242 			phy-connection-type = "rgmii-id";
246 			phy-handle = <&phy0>;
247 			tbi-handle = <&tbi1>;
248 			phy-connection-type = "sgmii";
252 			phy-handle = <&phy1>;
253 			phy-connection-type = "rgmii-id";
262 		reg = <0x0 0xffe09000 0x0 0x1000>;
277 		reg = <0x0 0xffe0a000 0x0 0x1000>;
292 /include/ "p1020si-post.dtsi"