Lines Matching +full:load +full:- +full:reserved
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
12 * Copyright (C) 2010-2011 Jonas Bonn <jonas@southpole.se>
25 #include <asm/asm-offsets.h>
46 l.sw -8(r1),r2 /* store frame pointer */ ;\
47 l.sw -4(r1),r9 /* store return address */ ;\
50 l.addi r1,r1,-8 ;\
52 l.lwz r9,-4(r1) /* restore return address */ ;\
53 l.lwz r2,-8(r1) /* restore fp */ ;\
59 l.sw -12(r1),t1 /* save extra reg */ ;\
60 l.sw -8(r1),r2 /* store frame pointer */ ;\
61 l.sw -4(r1),r9 /* store return address */ ;\
64 l.addi r1,r1,-12 ;\
66 l.lwz r9,-4(r1) /* restore return address */ ;\
67 l.lwz r2,-8(r1) /* restore fp */ ;\
68 l.lwz t1,-12(r1) /* restore extra reg */
178 /* Store -1 in orig_gpr11 for non-syscall exceptions */ ;\
179 l.addi r30,r0,-1 ;\
215 /* Store -1 in orig_gpr11 for non-syscall exceptions */ ;\
216 l.addi r30,r0,-1 ;\
244 /* ---[ 0x100: RESET exception ]----------------------------------------- */
250 /* ---[ 0x200: BUS exception ]------------------------------------------- */
261 /* ---[ 0x300: Data Page Fault exception ]------------------------------- */
335 /* ---[ 0x400: Insn Page Fault exception ]------------------------------- */
358 /* ---[ 0x500: Timer exception ]----------------------------------------- */
368 /* ---[ 0x600: Alignment exception ]-------------------------------------- */
381 // l.mfspr r2,r0,SPR_EEAR_BASE /* Load the effective address */
383 // l.mfspr r5,r0,SPR_EPCR_BASE /* Load the insn address */
386 l.lwz r3,0(r5) /* Load insn */
389 l.sfeqi r4,0x00 /* Check if the load/store insn is in delay slot */
409 l.lwz r3,4(r5) /* Load the real load/store insn */
420 l.lwz r3,4(r5) /* Load the real load/store insn */
422 l.add r4,r4,r1 /* Load the jump register value from the stack */
530 /* ---[ 0x700: Illegal insn exception ]---------------------------------- */
540 /* ---[ 0x800: External interrupt exception ]---------------------------- */
551 l.addi r1,r1,-0x8
579 /* ---[ 0x900: DTLB miss exception ]------------------------------------- */
582 /* ---[ 0xa00: ITLB miss exception ]------------------------------------- */
585 /* ---[ 0xb00: Range exception ]----------------------------------------- */
589 /* ---[ 0xc00: Syscall exception ]--------------------------------------- */
599 /* Upon syscall entry we just save the callee-saved registers
600 * and not the call-clobbered ones.
604 .string "syscall r9:0x%08x -> syscall(%ld) return %ld\0"
610 /* r3-r8 must be saved because syscall restart relies
618 * then load the original r4
633 /* r14-r28 (even) aren't touched by the syscall fast path below
674 * which does it in a round-about way.
683 l.sw -4(r1),r27
684 l.sw -8(r1),r11
686 l.sw -12(r1),r29
688 l.sw -16(r1),r29
692 l.addi r1,r1,-16
704 /* r30 is a callee-saved register so this should still hold the
706 * _syscall_trace_leave expects syscall result to be in pt_regs->r11.
712 /* This is where the exception-return code begins... interrupts need to be
732 * make sure that all the call-saved registers get into pt_regs
756 * registers with whatever garbage is in pt_regs -- that's OK because those
763 /* The assumption here is that the registers r14-r28 (even) are untouched and
775 /* r3-r8 are technically clobbered, but syscall restart needs these
792 /* Here we use r13-r19 (odd) as scratch regs */
842 * syscall that returns -ENOSYS and then return to the regular
847 l.addi r11,r0,-ENOSYS
851 /* ---[ 0xd00: Floating Point exception ]-------------------------------- */
863 /* ---[ 0xe00: Trap exception ]------------------------------------------ */
874 /* ---[ 0xf00: Reserved exception ]-------------------------------------- */
878 /* ---[ 0x1000: Reserved exception ]------------------------------------- */
882 /* ---[ 0x1100: Reserved exception ]------------------------------------- */
886 /* ---[ 0x1200: Reserved exception ]------------------------------------- */
890 /* ---[ 0x1300: Reserved exception ]------------------------------------- */
894 /* ---[ 0x1400: Reserved exception ]------------------------------------- */
898 /* ---[ 0x1500: Reserved exception ]------------------------------------- */
902 /* ---[ 0x1600: Reserved exception ]------------------------------------- */
906 /* ---[ 0x1700: Reserved exception ]------------------------------------- */
910 /* ---[ 0x1800: Reserved exception ]------------------------------------- */
914 /* ---[ 0x1900: Reserved exception ]------------------------------------- */
918 /* ---[ 0x1a00: Reserved exception ]------------------------------------- */
922 /* ---[ 0x1b00: Reserved exception ]------------------------------------- */
926 /* ---[ 0x1c00: Reserved exception ]------------------------------------- */
930 /* ---[ 0x1d00: Reserved exception ]------------------------------------- */
934 /* ---[ 0x1e00: Reserved exception ]------------------------------------- */
938 /* ---[ 0x1f00: Reserved exception ]------------------------------------- */
1025 /* The syscall fast path return expects call-saved registers
1026 * r14-r28 to be untouched, so we restore them here as they
1065 * register, then load the previous register values and only at the end call
1076 * way, we are a function call and only need to preserve the callee-saved
1087 l.addi r1,r1,-(INT_FRAME_SIZE)
1093 /* Save callee-saved registers to the new pt_regs */
1106 /* We use thread_info->ksp for storing the address of the above
1108 * to lose the value of thread_info->ksp, though, so store it as
1109 * pt_regs->sp so that we can easily restore it when we are made
1113 /* Save the old value of thread_info->ksp as pt_regs->sp */
1120 l.lwz r1,TI_KSP(r10) /* Load new stack pointer */
1122 /* Restore the old value of thread_info->ksp */
1134 /* Restore callee-saved registers */
1145 /* Unwind stack to pre-switch state */
1148 /* Return via the link-register back to where we 'came from', where
1154 l.lwz r3,TI_TASK(r3) /* Load 'prev' as schedule_tail arg */
1163 * These are all just wrappers that don't touch the link-register r9, so the
1168 /* fork requires that we save all the callee-saved registers because they
1212 /* This is a catch-all syscall for atomic instructions for the OpenRISC 1000.