mips/kernel/cps-vec.S

152 1:	PTR_L	t1, VPEBOOTCFG_PC(v1)
155 	jr	t1
211 	PTR_LA	t1, 1f
212 	jr.hb	t1
242 	sll	t1, ta1, VPECONF0_XTC_SHIFT
243 	or	t0, t0, t1
282 	ext	t1, t0, CM3_GCR_Cx_ID_CLUSTER_SHF, 8
284 	mul	t1, t1, t2
286 		v0, v0, t1
290 	li	t1, COREBOOTCFG_SIZE
291 	mul	t0, t0, t1
310 	mfc0	t1, CP0_MVPCONF0
311 	srl	t1, t1, MVPCONF0_PVPE_SHIFT
312 	andi	t1, t1, MVPCONF0_PVPE >> MVPCONF0_PVPE_SHIFT
313 	addiu	t1, t1, 1
316 	clz	t1, t1
318 	subu	t1, t2, t1
320 	sll	t1, t2, t1
321 	addiu	t1, t1, -1
325 	and	t9, t9, t1
329 	li	t1, VPEBOOTCFG_SIZE
330 	mul	v1, t9, t1
347 	PTR_LA	t1, mips_gcr_base
348 	PTR_L	t1, 0(t1)
349 	PTR_L	t1, GCR_CPC_BASE_OFS(t1)
351 	and	t1, t1, t2
353 	PTR_ADD	t1, t1, t2
356 	PTR_S	ta2, CPC_CL_VC_RUN_OFS(t1)
360 	PTR_S	ta2, CPC_CL_VC_STOP_OFS(t1)
375 	PTR_LA	t1, 1f
376 	jr.hb	t1
378 1:	mfc0	t1, CP0_MVPCONTROL
379 	ori	t1, t1, MVPCONTROL_VPC
380 	mtc0	t1, CP0_MVPCONTROL
415 	lw	t1, VPEBOOTCFG_PC(t0)
416 	mttc0	t1, CP0_TCRESTART
419 	lw	t1, VPEBOOTCFG_SP(t0)
420 	mttgpr	t1, sp
423 	lw	t1, VPEBOOTCFG_GP(t0)
424 	mttgpr	t1, gp
451 	li	t1, ~TCSTATUS_IXMT
452 	and	t0, t0, t1
471 	mfc0	t1, CP0_MVPCONTROL
472 	xori	t1, t1, MVPCONTROL_VPC
473 	mtc0	t1, CP0_MVPCONTROL
522 	 li	t1, 2
523 	sllv	t0, t1, t0
526 	_EXT	t1, v0, MIPS_CONF1_IS_SHF, MIPS_CONF1_IS_SZ
527 	xori	t2, t1, 0x7
530 	addiu	t1, t1, 1
531 	sllv	t1, t3, t1
532 1:	/* At this point t1 == I-cache sets per way */
535 	mul	t1, t1, t0
536 	mul	t1, t1, t2
539 	PTR_ADD	a1, a0, t1
549 	 li	t1, 2
550 	sllv	t0, t1, t0
553 	_EXT	t1, v0, MIPS_CONF1_DS_SHF, MIPS_CONF1_DS_SZ
554 	xori	t2, t1, 0x7
557 	addiu	t1, t1, 1
558 	sllv	t1, t3, t1
559 1:	/* At this point t1 == D-cache sets per way */
562 	mul	t1, t1, t0
563 	mul	t1, t1, t2
566 	PTR_ADDU a1, a0, t1
597 	psstate	t1
605 	psstate	t1