Lines Matching +full:64 +full:bit

52  * introducing 64 bit GCRs and all prior CM versions having 32 bit GCRs.
53 * However we may run a kernel built for MIPS32 on a system with 64 bit GCRs,
58 * It's set to 0 for 32-bit accesses and 1 for 64-bit accesses.
165 GCR_ACCESSOR_RO(64, 0x000, config)
173 GCR_ACCESSOR_RW(64, 0x008, base)
201 #define CM_GCR_ERR_CONTROL_L2_ECC_EN BIT(1)
202 #define CM_GCR_ERR_CONTROL_L2_ECC_SUPPORT BIT(0)
205 GCR_ACCESSOR_RW(64, 0x040, error_mask)
208 GCR_ACCESSOR_RW(64, 0x048, error_cause)
214 GCR_ACCESSOR_RW(64, 0x050, error_addr)
217 GCR_ACCESSOR_RW(64, 0x058, error_mult)
221 GCR_ACCESSOR_RW(64, 0x070, l2_only_sync_base)
223 #define CM_GCR_L2_ONLY_SYNC_BASE_SYNCEN BIT(0)
226 GCR_ACCESSOR_RW(64, 0x080, gic_base)
228 #define CM_GCR_GIC_BASE_GICEN BIT(0)
231 GCR_ACCESSOR_RW(64, 0x088, cpc_base)
233 #define CM_GCR_CPC_BASE_CPCEN BIT(0)
236 GCR_ACCESSOR_RW(64, 0x090, reg0_base)
237 GCR_ACCESSOR_RW(64, 0x0a0, reg1_base)
238 GCR_ACCESSOR_RW(64, 0x0b0, reg2_base)
239 GCR_ACCESSOR_RW(64, 0x0c0, reg3_base)
243 GCR_ACCESSOR_RW(64, 0x098, reg0_mask)
244 GCR_ACCESSOR_RW(64, 0x0a8, reg1_mask)
245 GCR_ACCESSOR_RW(64, 0x0b8, reg2_mask)
246 GCR_ACCESSOR_RW(64, 0x0c8, reg3_mask)
249 #define CM_GCR_REGn_MASK_CCAOVREN BIT(4)
250 #define CM_GCR_REGn_MASK_DROPL2 BIT(2)
259 #define CM_GCR_GIC_STATUS_EX BIT(0)
263 #define CM_GCR_CPC_STATUS_EX BIT(0)
271 #define CM_GCR_L2_CONFIG_BYPASS BIT(20)
281 GCR_ACCESSOR_RW(64, 0x240, l2_ram_config)
282 #define CM_GCR_L2_RAM_CONFIG_PRESENT BIT(31)
283 #define CM_GCR_L2_RAM_CONFIG_HCI_DONE BIT(30)
284 #define CM_GCR_L2_RAM_CONFIG_HCI_SUPPORTED BIT(29)
289 #define CM_GCR_L2_PFT_CONTROL_PFTEN BIT(8)
294 #define CM_GCR_L2_PFT_CONTROL_B_CEN BIT(8)
298 GCR_ACCESSOR_RW(64, 0x600, l2_tag_addr)
301 GCR_ACCESSOR_RW(64, 0x608, l2_tag_state)
304 GCR_ACCESSOR_RW(64, 0x610, l2_data)
307 GCR_ACCESSOR_RW(64, 0x618, l2_ecc)
311 #define CM_GCR_L2SM_COP_PRESENT BIT(31)
318 #define CM_GCR_L2SM_COP_RUNNING BIT(5)
332 GCR_ACCESSOR_RW(64, 0x628, l2sm_tag_addr_cop)
337 GCR_ACCESSOR_RW(64, 0x680, bev_base)
345 #define CM3_GCR_Cx_COHERENCE_COHEN BIT(0)
355 #define CM_GCR_Cx_OTHER_CLUSTER_EN BIT(31) /* CM >= 3.5 */
356 #define CM_GCR_Cx_OTHER_GIC_EN BIT(30) /* CM >= 3.5 */
369 GCR_CX_ACCESSOR_RW(64, 0x020, reset64_base)
372 #define CM_GCR_Cx_RESET_BASE_MODE BIT(1)
381 #define CM_GCR_Cx_RESET_EXT_BASE_EVARESET BIT(31)
382 #define CM_GCR_Cx_RESET_EXT_BASE_UEB BIT(30)
385 #define CM_GCR_Cx_RESET_EXT_BASE_PRESENT BIT(0)