Lines Matching +full:processor +full:- +full:b +full:- +full:side
1 # SPDX-License-Identifier: GPL-2.0
146 bool "Generic board-agnostic MIPS kernel"
203 bool "Alchemy processor based machines"
288 Build a generic DT-based kernel image that boots on select
289 BCM33xx cable modem chips, BCM63xx DSL chips, and BCM7xxx set-top
381 see the Linux/MIPS FAQ on <http://www.linux-mips.org/> and the
382 DECstation porting pages on <http://decstation.unix-ag.org/>.
421 Olivetti M700-10 workstations.
458 bool "Loongson 32-bit family of machines"
461 This enables support for the Loongson-1 family of machines.
463 Loongson-1 is a family of 32-bit MIPS-compatible SoCs developed by
468 bool "Loongson-2E/F family of machines"
471 This enables the support of early Loongson-2E/F family of machines.
474 bool "Loongson 64-bit family of machines"
509 This enables the support of Loongson-2/3 family of machines.
511 Loongson-2 and Loongson-3 are 64-bit general-purpose processors with
512 GS264/GS464/GS464E/GS464V microarchitecture (except old Loongson-2E
513 and Loongson-2F which will be removed), developed by the Institute
578 Microchip PIC32 is a family of general-purpose 32 bit MIPS core
776 This is the SGI Indigo2 with R10000 processor. To compile a Linux
833 bool "Sibyte BCM91125C-CRhone"
843 bool "Sibyte BCM91125E-Rhone"
852 bool "Sibyte BCM91250A-SWARM"
865 bool "Sibyte BCM91250C2-LittleSur"
877 bool "Sibyte BCM91250E-Sentosa"
887 bool "Sibyte BCM91480B-BigSur"
936 The SNI RM200/300/400 are MIPS-based machines manufactured by
1015 This requires u-boot on the platform.
1030 source "arch/mips/sgi-ip27/Kconfig"
1033 source "arch/mips/cavium-octeon/Kconfig"
1311 bool "Loongson 64-bit CPU"
1333 The Loongson GSx64(GS264/GS464/GS464E/GS464V) series of processor
1335 including most 64-bit Loongson-2 (2H, 2K) and Loongson-3 (3A1000,
1337 Loongson-2E/2F is not covered here and will be removed in future.
1344 The Loongson 2E processor implements the MIPS III instruction set
1355 The Loongson 2F processor implements the MIPS III instruction set
1358 Loongson2F have built-in DDR2 and PCIX controller. The PCIX controller
1363 bool "Loongson 1B"
1368 The Loongson 1B is a 32-bit SoC, which implements the MIPS32
1378 The Loongson 1C is a 32-bit SoC, which implements the MIPS32
1390 MIPS32 architecture. Most modern embedded systems with a 32-bit
1391 MIPS processor are based on a MIPS32 processor. If you know the
1392 specific type of processor in your system, choose those that one
1395 years so chances are you even have a MIPS32 Release 2 processor
1408 MIPS32 architecture. Most modern embedded systems with a 32-bit
1409 MIPS processor are based on a MIPS32 processor. If you know the
1410 specific type of processor in your system, choose those that one
1425 family, are based on a MIPS32r5 processor. If you own an older
1426 processor, you probably need to select MIPS32r1 or MIPS32r2 instead.
1441 family, are based on a MIPS32r6 processor. If you own an older
1442 processor, you probably need to select MIPS32r1 or MIPS32r2 instead.
1454 MIPS64 architecture. Many modern embedded systems with a 64-bit
1455 MIPS processor are based on a MIPS64 processor. If you know the
1456 specific type of processor in your system, choose those that one
1459 years so chances are you even have a MIPS64 Release 2 processor
1474 MIPS64 architecture. Many modern embedded systems with a 64-bit
1475 MIPS processor are based on a MIPS64 processor. If you know the
1476 specific type of processor in your system, choose those that one
1511 family, are based on a MIPS64r6 processor. If you own an older
1512 processor, you probably need to select MIPS64r1 or MIPS64r2 instead.
1529 MMU with two-levels TLB, UCA, MSA, MDU core level features and system
1531 cache, IOCU/IOMMU (though might be unused depending on the system-
1556 MIPS Technologies R4300-series processors.
1565 MIPS Technologies R4000-series processors other than 4300, including
1583 MIPS Technologies R5000-series processors other than the Nevada.
1592 NEC VR5500 and VR5500A series processors implement 64-bit MIPS IV
1602 QED / PMC-Sierra RM52xx-series ("Nevada") processors.
1613 MIPS Technologies R10000-series processors.
1634 bool "Cavium Octeon processor"
1648 The Cavium Octeon processor is a highly integrated chip containing
1649 many ethernet hardware widgets for networking tasks. The processor
1677 bool "New Loongson-3 CPU Enhancements"
1681 New Loongson-3 cores (since Loongson-3A R2, as opposed to Loongson-3A
1682 R1, Loongson-3B R1 and Loongson-3B R2) has many enhancements, such as
1683 FTLB, L1-VCache, EI/DI/Wait/Prefetch instruction, DSP/DSPr2 ASE, User
1684 Local register, Read-Inhibit/Execute-Inhibit, SFB (Store Fill Buffer),
1689 please say 'N' here. If you want a high-performance kernel to run on
1690 new Loongson-3 machines only, please say 'Y' here.
1693 bool "Loongson-3 LLSC Workarounds"
1697 Loongson-3 processors have the llsc issues which require workarounds.
1707 Loongson-3A R4 and newer have the CPUCFG instruction available for
1710 cores, back to Loongson-3A1000.
1758 than 40 bits. Note that this has the side effect of turning on
1759 64-bit addressing which in turn makes the PTEs 64-bit in size.
1778 -mfix-loongson2f-nop and -mfix-loongson2f-jump options.
1781 are needed. The workarounds have no significant side effect on them
1949 # CPU may reorder R->R, R->W, W->R, W->W
1957 # CPU may reorder R->LL, R->LL, W->LL, W->LL, R->SC, R->SC, W->SC, W->SC
2059 actually benefits from 64-bit processing or if your machine has
2061 menu if your system does not support both 32-bit and 64-bit kernels.
2064 bool "32-bit kernel"
2068 Select this option if you want to build a 32-bit kernel.
2071 bool "64-bit kernel"
2074 Select this option if you want to build a 64-bit kernel.
2099 This is only used if non-zero.
2126 # Support for a MIPS32 / MIPS64 style S-caches
2206 <http://www.imgtec.com/mips/mips-multithreading.asp>.
2227 bool "Dynamic FPU affinity for FP-intensive threads"
2232 bool "MIPS R2-to-R6 emulator"
2237 Choose this option if you want to run non-R6 MIPS userland code.
2240 The only reason this is a build-time option is to save ~14K from the
2412 # CPU non-features
2417 # - The `daddi' instruction fails to trap on overflow.
2418 # "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0",
2421 # - The `daddiu' instruction can produce an incorrect result.
2422 # "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0",
2424 # "MIPS R4000MC Errata, Processor Revision 2.2 and 3.0", erratum
2426 # "MIPS R4400PC/SC Errata, Processor Revision 1.0", erratum #7
2427 # "MIPS R4400MC Errata, Processor Revision 1.0", erratum #5
2433 # - A double-word or a variable shift may give an incorrect result
2435 # "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0",
2437 # "MIPS R4000MC Errata, Processor Revision 2.2 and 3.0", erratum
2440 # - A double-word or a variable shift may give an incorrect result
2442 # "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0",
2445 # - An integer division may give an incorrect result if started in
2447 # "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0",
2455 # - A double-word or a variable shift may give an incorrect result
2457 # "MIPS R4400MC Errata, Processor Revision 1.0", erratum #10
2458 # "MIPS R4400MC Errata, Processor Revision 2.0 & 3.0", erratum #4
2482 # interrupts during indexed I-cache flushes seems to be sufficient to deal
2534 # The RM7000 processors and the E9000 cores have a bug (though PMC-Sierra
2536 # I-cache line worth of instructions being fetched may case spurious
2542 # may cause ll / sc and lld / scd sequences to execute non-atomically.
2551 # - Highmem only makes sense for the 32-bit kernel.
2552 # - The current highmem code will only work properly on physically indexed
2559 # - We use SYS_SUPPORTS_HIGHMEM to offer highmem only for systems where we
2583 This option must be set if a kernel might be executed on a MIPS16-
2585 words, it makes the kernel MIPS16-tolerant.
2604 Say Y to compile the kernel to support NUMA (Non-Uniform Memory
2672 This is limited by the size of KSEG0, 256Mb on 32-bit or 1Gb with
2673 EVA or 64-bit. The default is 16Mb.
2700 bool "Multi-Processing support"
2707 If you say N here, the kernel will run on uni- and multiprocessor
2716 See also the SMP-HOWTO available at
2722 bool "Support for hot-pluggable CPUs"
2756 int "Maximum number of CPUs (2-256)"
2766 kernel will support. The maximum supported value is 32 for 32-bit
2767 kernel and 64 for 64-bit kernels; the minimum value which makes
2771 This is purely to save memory - each supported CPU adds
2891 passed to the panic-ed kernel).
2894 bool "Support for O32 binaries using 64-bit FP" if !CPU_MIPSR6
2897 When this is enabled, the kernel will support use of 64-bit floating
2899 EF_MIPS_FP64 ELF header flag (typically built with -mfp64). On
2900 32-bit MIPS systems this support is at the cost of increasing the
2903 will require 64-bit floating point, you may wish to reduce the size
2946 objcopy --update-section .appended_dtb=<filename>.dtb vmlinux
3041 <http://www.computer-refuge.org/classiccmp/ftp.digital.com/pub/DEC/TriAdd/>
3043 <http://www.linux-mips.org/wiki/DECstation>
3087 32-bit binaries as used by the 32-bit Linux/MIPS port. Most of
3100 64-bit binaries using 32-bit quantities for addressing and certain
3101 data that would normally be 64-bit. They are used in special
3108 depends on $(cc-option,-mno-branch-likely)
3110 # https://github.com/llvm/llvm-project/issues/61045