Lines Matching +full:0 +full:xff00000
23 #define dvma_malloc(x) dvma_malloc_align(x, 0)
24 #define dvma_map(x, y) dvma_map_align(x, y, 0)
25 #define dvma_map_vme(x, y) (dvma_map(x, y) & 0xfffff)
26 #define dvma_map_align_vme(x, y, z) (dvma_map_align (x, y, z) & 0xfffff)
41 #define DVMA_START 0xf00000
42 #define DVMA_END 0xfe0000
47 /* empirical kludge -- dvma regions only seem to work right on 0x10000
49 #define DVMA_REGION_SIZE 0x10000
54 #define dvma_vtop(x) ((unsigned long)(x) & 0xffffff)
55 #define dvma_ptov(x) ((unsigned long)(x) | 0xf000000)
56 #define dvma_vtovme(x) ((unsigned long)(x) & 0x00fffff)
57 #define dvma_vmetov(x) ((unsigned long)(x) | 0xff00000)
66 return 0; in dvma_map_cpu()
75 #define DVMA_START 0x0
76 #define DVMA_END 0xf00000
80 #define IOMMU_ENTRIES (IOMMU_TOTAL_ENTRIES - 0x80)
82 #define dvma_vtob(x) ((unsigned long)(x) & 0x00ffffff)
83 #define dvma_btov(x) ((unsigned long)(x) | 0xff000000)
143 #define DMA_DEVICE_ID 0xf0000000 /* Device identification bits */
144 #define DMA_VERS0 0x00000000 /* Sunray DMA version */
145 #define DMA_ESCV1 0x40000000 /* DMA ESC Version 1 */
146 #define DMA_VERS1 0x80000000 /* DMA rev 1 */
147 #define DMA_VERS2 0xa0000000 /* DMA rev 2 */
148 #define DMA_VERHME 0xb0000000 /* DMA hme gate array */
149 #define DMA_VERSPLUS 0x90000000 /* DMA rev 1 PLUS */
151 #define DMA_HNDL_INTR 0x00000001 /* An IRQ needs to be handled */
152 #define DMA_HNDL_ERROR 0x00000002 /* We need to take an error */
153 #define DMA_FIFO_ISDRAIN 0x0000000c /* The DMA FIFO is draining */
154 #define DMA_INT_ENAB 0x00000010 /* Turn on interrupts */
155 #define DMA_FIFO_INV 0x00000020 /* Invalidate the FIFO */
156 #define DMA_ACC_SZ_ERR 0x00000040 /* The access size was bad */
157 #define DMA_FIFO_STDRAIN 0x00000040 /* DMA_VERS1 Drain the FIFO */
158 #define DMA_RST_SCSI 0x00000080 /* Reset the SCSI controller */
160 #define DMA_ST_WRITE 0x00000100 /* write from device to memory */
161 #define DMA_ENABLE 0x00000200 /* Fire up DMA, handle requests */
162 #define DMA_PEND_READ 0x00000400 /* DMA_VERS1/0/PLUS Pending Read */
163 #define DMA_ESC_BURST 0x00000800 /* 1=16byte 0=32byte */
164 #define DMA_READ_AHEAD 0x00001800 /* DMA read ahead partial longword */
165 #define DMA_DSBL_RD_DRN 0x00001000 /* No EC drain on slave reads */
166 #define DMA_BCNT_ENAB 0x00002000 /* If on, use the byte counter */
167 #define DMA_TERM_CNTR 0x00004000 /* Terminal counter */
168 #define DMA_CSR_DISAB 0x00010000 /* No FIFO drains during csr */
169 #define DMA_SCSI_DISAB 0x00020000 /* No FIFO drains during reg */
170 #define DMA_DSBL_WR_INV 0x00020000 /* No EC inval. on slave writes */
171 #define DMA_ADD_ENABLE 0x00040000 /* Special ESC DVMA optimization */
172 #define DMA_E_BURST8 0x00040000 /* ENET: SBUS r/w burst size */
173 #define DMA_BRST_SZ 0x000c0000 /* SCSI: SBUS r/w burst size */
174 #define DMA_BRST64 0x00080000 /* SCSI: 64byte bursts (HME on UltraSparc only) */
175 #define DMA_BRST32 0x00040000 /* SCSI: 32byte bursts */
176 #define DMA_BRST16 0x00000000 /* SCSI: 16byte bursts */
177 #define DMA_BRST0 0x00080000 /* SCSI: no bursts (non-HME gate arrays) */
178 #define DMA_ADDR_DISAB 0x00100000 /* No FIFO drains during addr */
179 #define DMA_2CLKS 0x00200000 /* Each transfer = 2 clock ticks */
180 #define DMA_3CLKS 0x00400000 /* Each transfer = 3 clock ticks */
182 #define DMA_CNTR_DISAB 0x00800000 /* No IRQ when DMA_TERM_CNTR set */
183 #define DMA_AUTO_NADDR 0x01000000 /* Use "auto nxt addr" feature */
184 #define DMA_SCSI_ON 0x02000000 /* Enable SCSI dma */
185 #define DMA_PARITY_OFF 0x02000000 /* HME: disable parity checking */
186 #define DMA_LOADED_ADDR 0x04000000 /* Address has been loaded */
187 #define DMA_LOADED_NADDR 0x08000000 /* Next address has been loaded */
190 #define DMA_BURST1 0x01
191 #define DMA_BURST2 0x02
192 #define DMA_BURST4 0x04
193 #define DMA_BURST8 0x08
194 #define DMA_BURST16 0x10
195 #define DMA_BURST32 0x20
196 #define DMA_BURST64 0x40
197 #define DMA_BURSTBITS 0x7f
200 #define DMA_MAXEND(addr) (0x01000000UL-(((unsigned long)(addr))&0x00ffffffUL))
223 } while (0)
227 } while(0)
241 dma->running = 0; \
242 } while(0)