loongarch/mm/tlbex.S

1 /* SPDX-License-Identifier: GPL-2.0 */
3  * Copyright (C) 2020-2022 Loongson Technology Corporation Limited
14 #define PTRS_PER_PGD_BITS	(PAGE_SHIFT - 3)
15 #define PTRS_PER_PUD_BITS	(PAGE_SHIFT - 3)
16 #define PTRS_PER_PMD_BITS	(PAGE_SHIFT - 3)
17 #define PTRS_PER_PTE_BITS	(PAGE_SHIFT - 3)
63 	bstrpick.d	ra, t0, PTRS_PER_PGD_BITS + PGDIR_SHIFT - 1, PGDIR_SHIFT
64 	alsl.d		t1, ra, t1, 3
66 	ld.d		t1, t1, 0
67 	bstrpick.d	ra, t0, PTRS_PER_PUD_BITS + PUD_SHIFT - 1, PUD_SHIFT
68 	alsl.d		t1, ra, t1, 3
71 	ld.d		t1, t1, 0
72 	bstrpick.d	ra, t0, PTRS_PER_PMD_BITS + PMD_SHIFT - 1, PMD_SHIFT
73 	alsl.d		t1, ra, t1, 3
75 	ld.d		ra, t1, 0
78 	 * For huge tlb entries, pmde doesn't contain an address but
79 	 * instead contains the tlb pte. Check the PAGE_HUGE bit and
80 	 * see if we need to jump to huge tlb processing.
82 	rotri.d		ra, ra, _PAGE_HUGE_SHIFT + 1
85 	rotri.d		ra, ra, 64 - (_PAGE_HUGE_SHIFT + 1)
86 	bstrpick.d	t0, t0, PTRS_PER_PTE_BITS + PAGE_SHIFT - 1, PAGE_SHIFT
87 	alsl.d		t1, t0, ra, _PTE_T_LOG2
91 	ll.d		t0, t1, 0
93 	ld.d		t0, t1, 0
100 	sc.d		t0, t1, 0
103 	st.d		t0, t1, 0
106 	bstrins.d	t1, zero, 3, 3
107 	ld.d		t0, t1, 0
108 	ld.d		t1, t1, 8
127 	ll.d		ra, t1, 0
129 	rotri.d		ra, ra, 64 - (_PAGE_HUGE_SHIFT + 1)
136 	sc.d		t0, t1, 0
141 	st.d		t0, t1, 0
149 	 * A huge PTE describes an area the size of the
150 	 * configured huge page size. This is twice the
151 	 * of the large TLB entry size we intend to use.
152 	 * A TLB entry half the size of the configured
153 	 * huge page size is configured into entrylo0
161 	srli.d		t1, t1, (_PAGE_HGLOBAL_SHIFT - _PAGE_GLOBAL_SHIFT)
168 	addi.d		t1, zero, 1
169 	slli.d		t1, t1, (HPAGE_SHIFT - 1)
170 	add.d		t0, t0, t1
173 	/* Set huge page tlb entry size */
174 	addu16i.d	t0, zero, (CSR_TLBIDX_PS >> 16)
175 	addu16i.d	t1, zero, (PS_HUGE_SIZE << (CSR_TLBIDX_PS_SHIFT - 16))
180 	addu16i.d	t0, zero, (CSR_TLBIDX_PS >> 16)
181 	addu16i.d	t1, zero, (PS_DEFAULT_SIZE << (CSR_TLBIDX_PS_SHIFT - 16))
219 	bstrpick.d	ra, t0, PTRS_PER_PGD_BITS + PGDIR_SHIFT - 1, PGDIR_SHIFT
220 	alsl.d		t1, ra, t1, 3
222 	ld.d		t1, t1, 0
223 	bstrpick.d	ra, t0, PTRS_PER_PUD_BITS + PUD_SHIFT - 1, PUD_SHIFT
224 	alsl.d		t1, ra, t1, 3
227 	ld.d		t1, t1, 0
228 	bstrpick.d	ra, t0, PTRS_PER_PMD_BITS + PMD_SHIFT - 1, PMD_SHIFT
229 	alsl.d		t1, ra, t1, 3
231 	ld.d		ra, t1, 0
234 	 * For huge tlb entries, pmde doesn't contain an address but
235 	 * instead contains the tlb pte. Check the PAGE_HUGE bit and
236 	 * see if we need to jump to huge tlb processing.
238 	rotri.d		ra, ra, _PAGE_HUGE_SHIFT + 1
241 	rotri.d		ra, ra, 64 - (_PAGE_HUGE_SHIFT + 1)
242 	bstrpick.d	t0, t0, PTRS_PER_PTE_BITS + PAGE_SHIFT - 1, PAGE_SHIFT
243 	alsl.d		t1, t0, ra, _PTE_T_LOG2
247 	ll.d		t0, t1, 0
249 	ld.d		t0, t1, 0
257 	sc.d		t0, t1, 0
260 	st.d		t0, t1, 0
263 	bstrins.d	t1, zero, 3, 3
264 	ld.d		t0, t1, 0
265 	ld.d		t1, t1, 8
284 	ll.d		ra, t1, 0
286 	rotri.d		ra, ra, 64 - (_PAGE_HUGE_SHIFT + 1)
294 	sc.d		t0, t1, 0
299 	st.d		t0, t1, 0
307 	 * A huge PTE describes an area the size of the
308 	 * configured huge page size. This is twice the
309 	 * of the large TLB entry size we intend to use.
310 	 * A TLB entry half the size of the configured
311 	 * huge page size is configured into entrylo0
319 	srli.d		t1, t1, (_PAGE_HGLOBAL_SHIFT - _PAGE_GLOBAL_SHIFT)
326 	addi.d		t1, zero, 1
327 	slli.d		t1, t1, (HPAGE_SHIFT - 1)
328 	add.d		t0, t0, t1
331 	/* Set huge page tlb entry size */
332 	addu16i.d	t0, zero, (CSR_TLBIDX_PS >> 16)
333 	addu16i.d	t1, zero, (PS_HUGE_SIZE << (CSR_TLBIDX_PS_SHIFT - 16))
338 	/* Reset default page size */
339 	addu16i.d	t0, zero, (CSR_TLBIDX_PS >> 16)
340 	addu16i.d	t1, zero, (PS_DEFAULT_SIZE << (CSR_TLBIDX_PS_SHIFT - 16))
378 	bstrpick.d	ra, t0, PTRS_PER_PGD_BITS + PGDIR_SHIFT - 1, PGDIR_SHIFT
379 	alsl.d		t1, ra, t1, 3
381 	ld.d		t1, t1, 0
382 	bstrpick.d	ra, t0, PTRS_PER_PUD_BITS + PUD_SHIFT - 1, PUD_SHIFT
383 	alsl.d		t1, ra, t1, 3
386 	ld.d		t1, t1, 0
387 	bstrpick.d	ra, t0, PTRS_PER_PMD_BITS + PMD_SHIFT - 1, PMD_SHIFT
388 	alsl.d		t1, ra, t1, 3
390 	ld.d		ra, t1, 0
393 	 * For huge tlb entries, pmde doesn't contain an address but
394 	 * instead contains the tlb pte. Check the PAGE_HUGE bit and
395 	 * see if we need to jump to huge tlb processing.
397 	rotri.d		ra, ra, _PAGE_HUGE_SHIFT + 1
400 	rotri.d		ra, ra, 64 - (_PAGE_HUGE_SHIFT + 1)
401 	bstrpick.d	t0, t0, PTRS_PER_PTE_BITS + PAGE_SHIFT - 1, PAGE_SHIFT
402 	alsl.d		t1, t0, ra, _PTE_T_LOG2
406 	ll.d		t0, t1, 0
408 	ld.d		t0, t1, 0
415 	sc.d		t0, t1, 0
418 	st.d		t0, t1, 0
421 	bstrins.d	t1, zero, 3, 3
422 	ld.d		t0, t1, 0
423 	ld.d		t1, t1, 8
442 	ll.d		ra, t1, 0
444 	rotri.d		ra, ra, 64 - (_PAGE_HUGE_SHIFT + 1)
451 	sc.d		t0, t1, 0
456 	st.d		t0, t1, 0
464 	 * A huge PTE describes an area the size of the
465 	 * configured huge page size. This is twice the
466 	 * of the large TLB entry size we intend to use.
467 	 * A TLB entry half the size of the configured
468 	 * huge page size is configured into entrylo0
476 	srli.d		t1, t1, (_PAGE_HGLOBAL_SHIFT - _PAGE_GLOBAL_SHIFT)
483 	addi.d		t1, zero, 1
484 	slli.d		t1, t1, (HPAGE_SHIFT - 1)
485 	add.d		t0, t0, t1
488 	/* Set huge page tlb entry size */
489 	addu16i.d	t0, zero, (CSR_TLBIDX_PS >> 16)
490 	addu16i.d	t1, zero, (PS_HUGE_SIZE << (CSR_TLBIDX_PS_SHIFT - 16))
495 	/* Reset default page size */
496 	addu16i.d	t0, zero, (CSR_TLBIDX_PS >> 16)
497 	addu16i.d	t1, zero, (PS_DEFAULT_SIZE << (CSR_TLBIDX_PS_SHIFT - 16))