1 /* SPDX-License-Identifier: GPL-2.0 */
3  * Copyright (C) 2020-2022 Loongson Technology Corporation Limited
16 #define read_cpucfg(reg) __cpucfg(reg)  argument
170  * CPUCFG index area: 0x40000000 -- 0x400000ff
177 #define csr_read32(reg) __csrrd_w(reg)  argument
178 #define csr_read64(reg) __csrrd_d(reg)  argument
179 #define csr_write32(val, reg) __csrwr_w(val, reg)  argument
180 #define csr_write64(val, reg) __csrwr_d(val, reg)  argument
181 #define csr_xchg32(val, mask, reg) __csrxchg_w(val, mask, reg)  argument
182 #define csr_xchg64(val, mask, reg) __csrxchg_d(val, mask, reg)  argument
185 #define iocsr_read32(reg) __iocsrrd_w(reg)  argument
186 #define iocsr_read64(reg) __iocsrrd_d(reg)  argument
187 #define iocsr_write32(val, reg) __iocsrwr_w(val, reg)  argument
188 #define iocsr_write64(val, reg) __iocsrwr_d(val, reg)  argument
218 #define LOONGARCH_CSR_PRMD		0x1	/* Prev-exception mode info */
242 #define  CSR_ECFG_VS_SHIFT_END		(CSR_ECFG_VS_SHIFT + CSR_ECFG_VS_WIDTH - 1)
333 #define  CSR_GTLBC_TGID_SHIFT_END	(CSR_GTLBC_TGID_SHIFT + CSR_GTLBC_TGID_WIDTH - 1)
358 #define LOONGARCH_CSR_PGDL		0x19	/* Page table base address when VA[VALEN-1] = 0 */
360 #define LOONGARCH_CSR_PGDH		0x1a	/* Page table base address when VA[VALEN-1] = 1 */
461 /* Percpu-data base allocated KS3 statically */
492 #define  CSR_GSTAT_GID_SHIFT_END	(CSR_GSTAT_GID_SHIFT + CSR_GSTAT_GID_WIDTH - 1)
1422 #define EXCCODE_TLBNR		5	/* TLB Read-Inhibit exception */
1423 #define EXCCODE_TLBNX		6	/* TLB Execution-Inhibit exception */
1472 #define EXCCODE_INT_END		(EXCCODE_INT_START + EXCCODE_INT_NUM - 1)
1474 /* FPU Status Register Names */
1521 #define FPU_CSR_RD	0x300	/* towards -Infinity */