56 #define A64_LS_REG(Rt, Rn, Rm, size, type) \  argument
57 	aarch64_insn_gen_load_store_reg(Rt, Rn, Rm, \
232 #define A64_ADDSUB_SREG(sf, Rd, Rn, Rm, type) \  argument
233 	aarch64_insn_gen_add_sub_shifted_reg(Rd, Rn, Rm, 0, \
235 /* Rd = Rn OP Rm */
236 #define A64_ADD(sf, Rd, Rn, Rm)  A64_ADDSUB_SREG(sf, Rd, Rn, Rm, ADD)  argument
237 #define A64_SUB(sf, Rd, Rn, Rm)  A64_ADDSUB_SREG(sf, Rd, Rn, Rm, SUB)  argument
238 #define A64_SUBS(sf, Rd, Rn, Rm) A64_ADDSUB_SREG(sf, Rd, Rn, Rm, SUB_SETFLAGS)  argument
239 /* Rd = -Rm */
240 #define A64_NEG(sf, Rd, Rm) A64_SUB(sf, Rd, A64_ZR, Rm)  argument
241 /* Rn - Rm; set condition flags */
242 #define A64_CMP(sf, Rn, Rm) A64_SUBS(sf, A64_ZR, Rn, Rm)  argument
253 /* Rd = Rn OP Rm */
254 #define A64_DATA2(sf, Rd, Rn, Rm, type) aarch64_insn_gen_data2(Rd, Rn, Rm, \  argument
256 #define A64_UDIV(sf, Rd, Rn, Rm) A64_DATA2(sf, Rd, Rn, Rm, UDIV)  argument
257 #define A64_SDIV(sf, Rd, Rn, Rm) A64_DATA2(sf, Rd, Rn, Rm, SDIV)  argument
258 #define A64_LSLV(sf, Rd, Rn, Rm) A64_DATA2(sf, Rd, Rn, Rm, LSLV)  argument
259 #define A64_LSRV(sf, Rd, Rn, Rm) A64_DATA2(sf, Rd, Rn, Rm, LSRV)  argument
260 #define A64_ASRV(sf, Rd, Rn, Rm) A64_DATA2(sf, Rd, Rn, Rm, ASRV)  argument
263 /* Rd = Ra + Rn * Rm */
264 #define A64_MADD(sf, Rd, Ra, Rn, Rm) aarch64_insn_gen_data3(Rd, Ra, Rn, Rm, \  argument
266 /* Rd = Ra - Rn * Rm */
267 #define A64_MSUB(sf, Rd, Ra, Rn, Rm) aarch64_insn_gen_data3(Rd, Ra, Rn, Rm, \  argument
269 /* Rd = Rn * Rm */
270 #define A64_MUL(sf, Rd, Rn, Rm) A64_MADD(sf, Rd, A64_ZR, Rn, Rm)  argument
273 #define A64_LOGIC_SREG(sf, Rd, Rn, Rm, type) \  argument
274 	aarch64_insn_gen_logical_shifted_reg(Rd, Rn, Rm, 0, \
276 /* Rd = Rn OP Rm */
277 #define A64_AND(sf, Rd, Rn, Rm)  A64_LOGIC_SREG(sf, Rd, Rn, Rm, AND)  argument
278 #define A64_ORR(sf, Rd, Rn, Rm)  A64_LOGIC_SREG(sf, Rd, Rn, Rm, ORR)  argument
279 #define A64_EOR(sf, Rd, Rn, Rm)  A64_LOGIC_SREG(sf, Rd, Rn, Rm, EOR)  argument
280 #define A64_ANDS(sf, Rd, Rn, Rm) A64_LOGIC_SREG(sf, Rd, Rn, Rm, AND_SETFLAGS)  argument
281 /* Rn & Rm; set condition flags */
282 #define A64_TST(sf, Rn, Rm) A64_ANDS(sf, A64_ZR, Rn, Rm)  argument
283 /* Rd = ~Rm (alias of ORN with A64_ZR as Rn) */
284 #define A64_MVN(sf, Rd, Rm)  \  argument
285 	A64_LOGIC_SREG(sf, Rd, A64_ZR, Rm, ORN)