kvm/vgic/vgic-v3-nested.c

52  * as the L1 guest is in charge of provisioning the interrupts via its own
58  * - on L2 load: move the in-memory L1 vGIC configuration into a shadow,
66  *   running becomes visible to L1 in the VNCR-accessible registers.
70  *   targeting L1 and prepare the grand switcheroo.
72  * - on L2 exit: emulate the HW bit, and deactivate corresponding the L1
73  *   interrupt. The L0 active state will be cleared by the HW if the L1
79  * used as a handover point between L2 and L1.
81  * - on delivery of a MI to L0 while L2 is running: make the L1 MI pending,
82  *   and let it rip. This will initiate a vcpu_put() on L2, and allow L1 to
85  * - L1 MI is a fully virtual interrupt, not linked to the host's MI. Its
90  *   quality of emulation is poor: L1 can setup the vgic so that an MI would
98  * - those backed by memory (LRs, APRs, HCR, VMCR): L1 can freely access
104  * Only L1 can access the ICH_*_EL2 registers. A non-NV L2 obviously cannot,
105  * and a NV L2 would either access the VNCR page provided by L1 (memory
106  * based registers), or see the access redirected to L1 (registers that
107  * trap) thanks to NV being set by L1.
386  * then we need to forward this to L1 so that it can re-sync the appropriate
393 	/* This will force a switch back to L1 if the level is high */  in vgic_v3_handle_nested_maint_irq()