arm64/kernel/entry.S

34 	.irp	n,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29
42 	.if	\el == 0
66 	tbnz	x0, #THREAD_SHIFT, 0f
71 0:
127 	nop					// Patched to SMC/HVC #0
200 	.if	\el == 0
206 	stp	x0, x1, [sp, #16 * 0]
220 	stp	x28, x29, [sp, #16 * 14]
222 	.if	\el == 0
282 	.endif /* \el == 0 */
292 	.if \el == 0
298 	add	x29, sp, #S_STACKFRAME
309 	.if	\el == 0
338 	.if	\el != 0
366 	.if	\el == 0
375 	mrs	x29, contextidr_el1
376 	msr	contextidr_el1, x29
411 	apply_ssbd 0, x0, x1
416 	ldp	x0, x1, [sp, #16 * 0]
430 	ldp	x28, x29, [sp, #16 * 14]
432 	.if	\el == 0
436 	msr	far_el1, x29
438 	ldr_this_cpu	x30, this_cpu_vector, x29
439 	tramp_alias	x29, tramp_exit
443 	br		x29
452 	.if \el == 0
494 1:	and	x22, x22, #~PSR_PAN_BIT		// ARMv8.0 CPUs do not understand this bit
532 	kernel_ventry	0, t, 64, sync		// Synchronous 64-bit EL0
533 	kernel_ventry	0, t, 64, irq		// IRQ 64-bit EL0
534 	kernel_ventry	0, t, 64, fiq		// FIQ 64-bit EL0
535 	kernel_ventry	0, t, 64, error		// Error 64-bit EL0
537 	kernel_ventry	0, t, 32, sync		// Synchronous 32-bit EL0
538 	kernel_ventry	0, t, 32, irq		// IRQ 32-bit EL0
539 	kernel_ventry	0, t, 32, fiq		// FIQ 32-bit EL0
540 	kernel_ventry	0, t, 32, error		// Error 32-bit EL0
579 	.if \el == 0
600 	entry_handler	0, t, 64, sync
601 	entry_handler	0, t, 64, irq
602 	entry_handler	0, t, 64, fiq
603 	entry_handler	0, t, 64, error
605 	entry_handler	0, t, 32, sync
606 	entry_handler	0, t, 32, irq
607 	entry_handler	0, t, 32, fiq
608 	entry_handler	0, t, 32, error
620 	kernel_exit 0
675 	 * instruction to load the upper 16 bits (which must be 0xFFFF).
683 #define BHB_MITIGATION_NONE	0
746 	.space	0x400
774 	tramp_unmap_kernel	x29
775 	mrs		x29, far_el1		// restore x29
799 	tramp_ventry	.Lvector_start\@, 64, 0, \bhb
802 	tramp_ventry	.Lvector_start\@, 32, 0, \bhb
836 	stp	x29, x9, [x8], #16
844 	ldp	x29, x9, [x8], #16
884 	stp	x29, x30, [sp, #-16]!
885 	mov	x29, sp
897 	mov	sp, x29
898 	ldp	x29, x30, [sp], #16
913 	smc	#0
915 99:	hvc	#0
992 	stp     x28, x29, [x1, #SDEI_EVENT_INTREGS + 16 * 14]
1039 	and     x0, x3, #0xc
1042 	csel	x29, x29, xzr, eq	// fp, or zero
1045 	stp	x29, x4, [sp, #-16]!
1046 	mov	x29, sp
1055 	ldp	x28, x29, [x4, #SDEI_EVENT_INTREGS + 16 * 14]