Lines Matching +full:4 +full:- +full:cpu
1 // SPDX-License-Identifier: GPL-2.0-only
3 * Contains CPU feature definitions
9 * there's a little bit of over-abstraction that tends to obscure what's going
14 * user-visible instructions are available only on a subset of the available
16 * boot CPU and comparing these with the feature registers of each secondary
17 * CPU when bringing them up. If there is a mismatch, then we update the
18 * snapshot state to indicate the lowest-common denominator of the feature,
27 * may prevent a CPU from being onlined at all.
31 * - Mismatched features are *always* sanitised to a "safe" value, which
34 * - A mismatched feature marked with FTR_STRICT will cause a "SANITY CHECK"
35 * warning when onlining an offending CPU and the kernel will be tainted
38 * - Features marked as FTR_VISIBLE have their sanitised value visible to
43 * - A "feature" is typically a 4-bit register field. A "capability" is the
44 * high-level description derived from the sanitised field value.
46 * - Read the Arm ARM (DDI 0487F.a) section D13.1.3 ("Principles of the ID
50 * - KVM exposes its own view of the feature registers to guest operating
57 * - If the arm64_ftr_bits[] for a register has a missing field, then this
63 #define pr_fmt(fmt) "CPU features: " fmt
75 #include <linux/cpu.h>
80 #include <asm/cpu.h>
120 * after the MMU (with the idmap) was enabled. create_init_idmap() - which
121 * runs before early_map_kernel() and reads the variable via PTE_MAYBE_NG -
130 * Permit PER_LINUX32 and execve() of 32-bit binaries even if not all CPUs
137 * seen at least one CPU capable of 32-bit EL0.
142 * Mask of CPUs supporting 32-bit EL0.
149 /* file-wide pr_fmt adds "CPU features: " prefix */ in dump_cpu_features()
155 BIT(reg##_##field##_WIDTH - 1) : \
156 BIT(reg##_##field##_WIDTH)) - 1)
158 #define __ARM64_MIN_NEGATIVE(reg, field) BIT(reg##_##field##_WIDTH - 1)
170 * an implicit maximum that depends on the sign-ess of the field.
183 * matching a non-implemented property.
220 * sync with the documentation of the CPU feature register ABI.
223 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_RNDR_SHIFT, 4, 0),
224 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_TLB_SHIFT, 4, 0),
225 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_TS_SHIFT, 4, 0),
226 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_FHM_SHIFT, 4, 0),
227 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_DP_SHIFT, 4, 0),
228 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SM4_SHIFT, 4, 0),
229 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SM3_SHIFT, 4, 0),
230 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SHA3_SHIFT, 4, 0),
231 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_RDM_SHIFT, 4, 0),
232 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_ATOMIC_SHIFT, 4, 0),
233 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_CRC32_SHIFT, 4, 0),
234 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SHA2_SHIFT, 4, 0),
235 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SHA1_SHIFT, 4, 0),
236 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_AES_SHIFT, 4, 0),
241 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_XS_SHIFT, 4, 0),
242 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_I8MM_SHIFT, 4, 0),
243 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_DGH_SHIFT, 4, 0),
244 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_BF16_SHIFT, 4, 0),
245 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_SPECRES_SHIFT, 4, 0),
246 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_SB_SHIFT, 4, 0),
247 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_FRINTTS_SHIFT, 4, 0),
249 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_GPI_SHIFT, 4, 0),
251 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_GPA_SHIFT, 4, 0),
252 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_LRCPC_SHIFT, 4, 0),
253 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_FCMA_SHIFT, 4, 0),
254 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_JSCVT_SHIFT, 4, 0),
256 FTR_STRICT, FTR_EXACT, ID_AA64ISAR1_EL1_API_SHIFT, 4, 0),
258 FTR_STRICT, FTR_EXACT, ID_AA64ISAR1_EL1_APA_SHIFT, 4, 0),
259 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_DPB_SHIFT, 4, 0),
264 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_LUT_SHIFT, 4, 0),
265 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_CSSC_SHIFT, 4, 0),
266 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_RPRFM_SHIFT, 4, 0),
267 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_CLRBHB_SHIFT, 4, 0),
268 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_BC_SHIFT, 4, 0),
269 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_MOPS_SHIFT, 4, 0),
271 FTR_STRICT, FTR_EXACT, ID_AA64ISAR2_EL1_APA3_SHIFT, 4, 0),
273 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_GPA3_SHIFT, 4, 0),
274 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_RPRES_SHIFT, 4, 0),
275 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_WFxT_SHIFT, 4, 0),
280 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR3_EL1_FPRCVT_SHIFT, 4, 0),
281 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR3_EL1_FAMINMAX_SHIFT, 4, 0),
286 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_CSV3_SHIFT, 4, 0),
287 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_CSV2_SHIFT, 4, 0),
288 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_DIT_SHIFT, 4, 0),
289 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_AMU_SHIFT, 4, 0),
290 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_MPAM_SHIFT, 4, 0),
291 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_SEL2_SHIFT, 4, 0),
293 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_SVE_SHIFT, 4, 0),
294 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_RAS_SHIFT, 4, 0),
295 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_GIC_SHIFT, 4, 0),
296 …S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_AdvSIMD_SHIFT, 4, ID_AA6…
297 …S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_FP_SHIFT, 4, ID_AA64PFR0…
298 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_EL3_SHIFT, 4, 0),
299 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_EL2_SHIFT, 4, 0),
300 …ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_EL1_SHIFT, 4, ID_AA64PFR…
301 …ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_EL0_SHIFT, 4, ID_AA64PFR…
307 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_GCS_SHIFT, 4, 0),
309 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_SME_SHIFT, 4, 0),
310 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_MPAM_frac_SHIFT, 4, 0),
311 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_RAS_frac_SHIFT, 4, 0),
313 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_MTE_SHIFT, 4, ID_AA64PFR1_EL1_MTE_NI),
314 …ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_SSBS_SHIFT, 4, ID_AA64P…
316 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_BT_SHIFT, 4, 0),
321 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR2_EL1_FPMR_SHIFT, 4, 0),
327 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_F64MM_SHIFT, 4, 0),
329 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_F32MM_SHIFT, 4, 0),
331 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_F16MM_SHIFT, 4, 0),
333 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_I8MM_SHIFT, 4, 0),
335 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_SM4_SHIFT, 4, 0),
337 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_SHA3_SHIFT, 4, 0),
339 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_B16B16_SHIFT, 4, 0),
341 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_BF16_SHIFT, 4, 0),
343 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_BitPerm_SHIFT, 4, 0),
345 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_EltPerm_SHIFT, 4, 0),
347 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_AES_SHIFT, 4, 0),
349 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_SVEver_SHIFT, 4, 0),
359 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_SMEver_SHIFT, 4, 0),
361 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_I16I64_SHIFT, 4, 0),
365 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_I16I32_SHIFT, 4, 0),
375 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_I8I32_SHIFT, 4, 0),
416 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_ECV_SHIFT, 4, 0),
417 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_FGT_SHIFT, 4, 0),
418 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_EXS_SHIFT, 4, 0),
420 * Page size not being supported at Stage-2 is not fatal. You
425 * advertises a given granule size at Stage-2 (value 2) on some
426 * vCPUs, and uses the fallback to Stage-1 (value 0) for other
434 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_EL1_TGRAN4_2_SHIFT, 4, 1),
435 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_EL1_TGRAN64_2_SHIFT, 4, 1),
436 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_EL1_TGRAN16_2_SHIFT, 4, 1),
442 * along with it and treat them as non-strict.
444 …S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_TGRAN4_SHIFT, 4, ID_A…
445 …S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_TGRAN64_SHIFT, 4, ID_…
446 …ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_TGRAN16_SHIFT, 4, ID_AA…
448 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_BIGENDEL0_SHIFT, 4, 0),
450 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_SNSMEM_SHIFT, 4, 0),
451 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_BIGEND_SHIFT, 4, 0),
452 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_ASIDBITS_SHIFT, 4, 0),
457 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_PARANGE_SHIFT, 4, 0),
462 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_ECBHB_SHIFT, 4, 0),
463 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_TIDCP1_SHIFT, 4, 0),
464 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_AFP_SHIFT, 4, 0),
465 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_HCX_SHIFT, 4, 0),
466 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_ETS_SHIFT, 4, 0),
467 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_TWED_SHIFT, 4, 0),
468 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_XNX_SHIFT, 4, 0),
469 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_HIGHER_SAFE, ID_AA64MMFR1_EL1_SpecSEI_SHIFT, 4, 0),
470 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_PAN_SHIFT, 4, 0),
471 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_LO_SHIFT, 4, 0),
472 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_HPDS_SHIFT, 4, 0),
473 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_VH_SHIFT, 4, 0),
474 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_VMIDBits_SHIFT, 4, 0),
475 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_HAFDBS_SHIFT, 4, 0),
480 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_E0PD_SHIFT, 4, 0),
481 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_EVT_SHIFT, 4, 0),
482 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_BBM_SHIFT, 4, 0),
483 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_TTL_SHIFT, 4, 0),
484 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_FWB_SHIFT, 4, 0),
485 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_IDS_SHIFT, 4, 0),
486 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_AT_SHIFT, 4, 0),
487 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_ST_SHIFT, 4, 0),
488 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_NV_SHIFT, 4, 0),
489 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_CCIDX_SHIFT, 4, 0),
490 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_VARange_SHIFT, 4, 0),
491 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_IESB_SHIFT, 4, 0),
492 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_LSM_SHIFT, 4, 0),
493 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_UAO_SHIFT, 4, 0),
494 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_CnP_SHIFT, 4, 0),
500 FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR3_EL1_S1POE_SHIFT, 4, 0),
501 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR3_EL1_S1PIE_SHIFT, 4, 0),
502 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR3_EL1_TCRX_SHIFT, 4, 0),
507 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR4_EL1_E2H0_SHIFT, 4, 0),
508 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR4_EL1_NV_frac_SHIFT, 4, 0),
516 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, CTR_EL0_CWG_SHIFT, 4, 0),
517 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, CTR_EL0_ERG_SHIFT, 4, 0),
518 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_EL0_DminLine_SHIFT, 4, 1),
520 * Linux can handle differing I-cache policies. Userspace JITs will
522 * If we have differing I-cache policies, report it as the weakest - VIPT.
525 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_EL0_IminLine_SHIFT, 4, 0),
538 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_InnerShr_SHIFT, 4, 0xf),
539 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_FCSE_SHIFT, 4, 0),
540 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_AuxReg_SHIFT, 4, 0),
541 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_TCM_SHIFT, 4, 0),
542 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_ShareLvl_SHIFT, 4, 0),
543 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_OuterShr_SHIFT, 4, 0xf),
544 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_PMSA_SHIFT, 4, 0),
545 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_VMSA_SHIFT, 4, 0),
550 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_EL1_DoubleLock_SHIFT, 4, 0),
551 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64DFR0_EL1_PMSVer_SHIFT, 4, 0),
552 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_EL1_CTX_CMPs_SHIFT, 4, 0),
553 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_EL1_WRPs_SHIFT, 4, 0),
554 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_EL1_BRPs_SHIFT, 4, 0),
559 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64DFR0_EL1_PMUVer_SHIFT, 4, 0),
560 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64DFR0_EL1_DebugVer_SHIFT, 4, 0x6),
565 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPRound_SHIFT, 4, 0),
566 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPShVec_SHIFT, 4, 0),
567 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPSqrt_SHIFT, 4, 0),
568 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPDivide_SHIFT, 4, 0),
569 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPTrap_SHIFT, 4, 0),
570 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPDP_SHIFT, 4, 0),
571 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPSP_SHIFT, 4, 0),
572 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_SIMDReg_SHIFT, 4, 0),
577 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_SIMDFMAC_SHIFT, 4, 0),
578 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_FPHP_SHIFT, 4, 0),
579 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_SIMDHP_SHIFT, 4, 0),
580 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_SIMDSP_SHIFT, 4, 0),
581 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_SIMDInt_SHIFT, 4, 0),
582 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_SIMDLS_SHIFT, 4, 0),
583 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_FPDNaN_SHIFT, 4, 0),
584 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_FPFtZ_SHIFT, 4, 0),
589 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR2_EL1_FPMisc_SHIFT, 4, 0),
590 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR2_EL1_SIMDMisc_SHIFT, 4, 0),
596 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, DCZID_EL0_BS_SHIFT, 4, 0),
601 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, GMID_EL1_BS_SHIFT, 4, 0),
606 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_Divide_SHIFT, 4, 0),
607 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_Debug_SHIFT, 4, 0),
608 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_Coproc_SHIFT, 4, 0),
609 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_CmpBranch_SHIFT, 4, 0),
610 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_BitField_SHIFT, 4, 0),
611 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_BitCount_SHIFT, 4, 0),
612 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_Swap_SHIFT, 4, 0),
617 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_RDM_SHIFT, 4, 0),
618 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_CRC32_SHIFT, 4, 0),
619 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_SHA2_SHIFT, 4, 0),
620 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_SHA1_SHIFT, 4, 0),
621 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_AES_SHIFT, 4, 0),
622 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_SEVL_SHIFT, 4, 0),
627 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_EVT_SHIFT, 4, 0),
628 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_CCIDX_SHIFT, 4, 0),
629 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_LSM_SHIFT, 4, 0),
630 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_HPDS_SHIFT, 4, 0),
631 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_CnP_SHIFT, 4, 0),
632 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_XNX_SHIFT, 4, 0),
633 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_AC2_SHIFT, 4, 0),
641 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_HIGHER_SAFE, ID_MMFR4_EL1_SpecSEI_SHIFT, 4, 0),
646 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_SWP_frac_SHIFT, 4, 0),
647 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_PSR_M_SHIFT, 4, 0),
648 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_SynchPrim_frac_SHIFT, 4, 0),
649 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_Barrier_SHIFT, 4, 0),
650 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_SMC_SHIFT, 4, 0),
651 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_Writeback_SHIFT, 4, 0),
652 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_WithShifts_SHIFT, 4, 0),
653 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_Unpriv_SHIFT, 4, 0),
658 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR5_EL1_ETS_SHIFT, 4, 0),
663 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_I8MM_SHIFT, 4, 0),
664 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_BF16_SHIFT, 4, 0),
665 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_SPECRES_SHIFT, 4, 0),
666 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_SB_SHIFT, 4, 0),
667 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_FHM_SHIFT, 4, 0),
668 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_DP_SHIFT, 4, 0),
669 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_JSCVT_SHIFT, 4, 0),
674 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_DIT_SHIFT, 4, 0),
675 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_CSV2_SHIFT, 4, 0),
676 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_State3_SHIFT, 4, 0),
677 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_State2_SHIFT, 4, 0),
678 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_State1_SHIFT, 4, 0),
679 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_State0_SHIFT, 4, 0),
684 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_GIC_SHIFT, 4, 0),
685 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_Virt_frac_SHIFT, 4, 0),
686 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_Sec_frac_SHIFT, 4, 0),
687 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_GenTimer_SHIFT, 4, 0),
688 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_Virtualization_SHIFT, 4, 0),
689 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_MProgMod_SHIFT, 4, 0),
690 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_Security_SHIFT, 4, 0),
691 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_ProgMod_SHIFT, 4, 0),
696 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR2_EL1_SSBS_SHIFT, 4, 0),
697 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR2_EL1_CSV3_SHIFT, 4, 0),
703 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_DFR0_EL1_PerfMon_SHIFT, 4, 0),
704 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_MProfDbg_SHIFT, 4, 0),
705 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_MMapTrc_SHIFT, 4, 0),
706 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_CopTrc_SHIFT, 4, 0),
707 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_MMapDbg_SHIFT, 4, 0),
708 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_CopSDbg_SHIFT, 4, 0),
709 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_CopDbg_SHIFT, 4, 0),
714 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR1_EL1_MTPMU_SHIFT, 4, 0),
728 * attributes, with 4bit feature fields and a default safe value of
730 * id_isar[1-3], id_mmfr[1-3]
733 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0),
734 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0),
735 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0),
736 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0),
737 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0),
738 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0),
739 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),
740 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),
812 /* Op1 = 0, CRn = 0, CRm = 4 */
846 /* Op1 = 0, CRn = 10, CRm = 4 */
862 return (int)(unsigned long)id - (int)((const struct __ftr_reg_entry *)regp)->sys_id; in search_cmp_ftr_reg()
866 * get_arm64_ftr_reg_nowarn - Looks up a feature register entry using
871 * returns - Upon success, matching ftr_reg entry for id.
872 * - NULL on failure. It is upto the caller to decide
885 return ret->reg; in get_arm64_ftr_reg_nowarn()
890 * get_arm64_ftr_reg - Looks up a feature register entry using
893 * returns - Upon success, matching ftr_reg entry for id.
894 * - NULL on failure but with an WARN_ON().
903 * Requesting a non-existent register search is an error. Warn in get_arm64_ftr_reg()
916 reg |= (ftr_val << ftrp->shift) & mask; in arm64_ftr_set_value()
925 switch (ftrp->type) { in arm64_ftr_safe_value()
927 ret = ftrp->safe_val; in arm64_ftr_safe_value()
952 const struct arm64_ftr_bits *ftr_bits = ftr_reg->ftr_bits; in sort_ftr_regs()
959 for (; ftr_bits->width != 0; ftr_bits++, j++) { in sort_ftr_regs()
960 unsigned int width = ftr_reg->ftr_bits[j].width; in sort_ftr_regs()
961 unsigned int shift = ftr_reg->ftr_bits[j].shift; in sort_ftr_regs()
966 ftr_reg->name, shift); in sort_ftr_regs()
975 prev_shift = ftr_reg->ftr_bits[j - 1].shift; in sort_ftr_regs()
978 ftr_reg->name, shift); in sort_ftr_regs()
992 BUG_ON(arm64_ftr_regs[i].sys_id <= arm64_ftr_regs[i - 1].sys_id); in sort_ftr_regs()
997 * Initialise the CPU feature register from Boot CPU values.
1000 * RES0 for the system-wide value, and must strictly match.
1015 for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) { in init_cpu_ftr_reg()
1018 s64 ftr_ovr = arm64_ftr_value(ftrp, reg->override->val); in init_cpu_ftr_reg()
1020 if ((ftr_mask & reg->override->mask) == ftr_mask) { in init_cpu_ftr_reg()
1026 reg->override->mask &= ~ftr_mask; in init_cpu_ftr_reg()
1027 reg->override->val &= ~ftr_mask; in init_cpu_ftr_reg()
1040 reg->name, in init_cpu_ftr_reg()
1041 ftrp->shift + ftrp->width - 1, in init_cpu_ftr_reg()
1042 ftrp->shift, str, in init_cpu_ftr_reg()
1043 tmp & (BIT(ftrp->width) - 1)); in init_cpu_ftr_reg()
1044 } else if ((ftr_mask & reg->override->val) == ftr_mask) { in init_cpu_ftr_reg()
1045 reg->override->val &= ~ftr_mask; in init_cpu_ftr_reg()
1047 reg->name, in init_cpu_ftr_reg()
1048 ftrp->shift + ftrp->width - 1, in init_cpu_ftr_reg()
1049 ftrp->shift); in init_cpu_ftr_reg()
1055 if (!ftrp->strict) in init_cpu_ftr_reg()
1057 if (ftrp->visible) in init_cpu_ftr_reg()
1060 reg->user_val = arm64_ftr_set_value(ftrp, in init_cpu_ftr_reg()
1061 reg->user_val, in init_cpu_ftr_reg()
1062 ftrp->safe_val); in init_cpu_ftr_reg()
1067 reg->sys_val = val; in init_cpu_ftr_reg()
1068 reg->strict_mask = strict_mask; in init_cpu_ftr_reg()
1069 reg->user_mask = user_mask; in init_cpu_ftr_reg()
1078 for (; caps->matches; caps++) { in init_cpucap_indirect_list_from_array()
1079 if (WARN(caps->capability >= ARM64_NCAPS, in init_cpucap_indirect_list_from_array()
1080 "Invalid capability %d\n", caps->capability)) in init_cpucap_indirect_list_from_array()
1082 if (WARN(cpucap_ptrs[caps->capability], in init_cpucap_indirect_list_from_array()
1084 caps->capability)) in init_cpucap_indirect_list_from_array()
1086 cpucap_ptrs[caps->capability] = caps; in init_cpucap_indirect_list_from_array()
1100 init_cpu_ftr_reg(SYS_ID_DFR0_EL1, info->reg_id_dfr0); in init_32bit_cpu_features()
1101 init_cpu_ftr_reg(SYS_ID_DFR1_EL1, info->reg_id_dfr1); in init_32bit_cpu_features()
1102 init_cpu_ftr_reg(SYS_ID_ISAR0_EL1, info->reg_id_isar0); in init_32bit_cpu_features()
1103 init_cpu_ftr_reg(SYS_ID_ISAR1_EL1, info->reg_id_isar1); in init_32bit_cpu_features()
1104 init_cpu_ftr_reg(SYS_ID_ISAR2_EL1, info->reg_id_isar2); in init_32bit_cpu_features()
1105 init_cpu_ftr_reg(SYS_ID_ISAR3_EL1, info->reg_id_isar3); in init_32bit_cpu_features()
1106 init_cpu_ftr_reg(SYS_ID_ISAR4_EL1, info->reg_id_isar4); in init_32bit_cpu_features()
1107 init_cpu_ftr_reg(SYS_ID_ISAR5_EL1, info->reg_id_isar5); in init_32bit_cpu_features()
1108 init_cpu_ftr_reg(SYS_ID_ISAR6_EL1, info->reg_id_isar6); in init_32bit_cpu_features()
1109 init_cpu_ftr_reg(SYS_ID_MMFR0_EL1, info->reg_id_mmfr0); in init_32bit_cpu_features()
1110 init_cpu_ftr_reg(SYS_ID_MMFR1_EL1, info->reg_id_mmfr1); in init_32bit_cpu_features()
1111 init_cpu_ftr_reg(SYS_ID_MMFR2_EL1, info->reg_id_mmfr2); in init_32bit_cpu_features()
1112 init_cpu_ftr_reg(SYS_ID_MMFR3_EL1, info->reg_id_mmfr3); in init_32bit_cpu_features()
1113 init_cpu_ftr_reg(SYS_ID_MMFR4_EL1, info->reg_id_mmfr4); in init_32bit_cpu_features()
1114 init_cpu_ftr_reg(SYS_ID_MMFR5_EL1, info->reg_id_mmfr5); in init_32bit_cpu_features()
1115 init_cpu_ftr_reg(SYS_ID_PFR0_EL1, info->reg_id_pfr0); in init_32bit_cpu_features()
1116 init_cpu_ftr_reg(SYS_ID_PFR1_EL1, info->reg_id_pfr1); in init_32bit_cpu_features()
1117 init_cpu_ftr_reg(SYS_ID_PFR2_EL1, info->reg_id_pfr2); in init_32bit_cpu_features()
1118 init_cpu_ftr_reg(SYS_MVFR0_EL1, info->reg_mvfr0); in init_32bit_cpu_features()
1119 init_cpu_ftr_reg(SYS_MVFR1_EL1, info->reg_mvfr1); in init_32bit_cpu_features()
1120 init_cpu_ftr_reg(SYS_MVFR2_EL1, info->reg_mvfr2); in init_32bit_cpu_features()
1143 np = of_find_compatible_node(NULL, NULL, "arm,gic-v3"); in detect_system_supports_pseudo_nmi()
1144 if (np && of_property_read_bool(np, "mediatek,broken-save-restore-fw")) { in detect_system_supports_pseudo_nmi()
1145 pr_info("Pseudo-NMI disabled due to MediaTek Chromebook GICR save problem\n"); in detect_system_supports_pseudo_nmi()
1159 init_cpu_ftr_reg(SYS_CTR_EL0, info->reg_ctr); in init_cpu_features()
1160 init_cpu_ftr_reg(SYS_DCZID_EL0, info->reg_dczid); in init_cpu_features()
1161 init_cpu_ftr_reg(SYS_CNTFRQ_EL0, info->reg_cntfrq); in init_cpu_features()
1162 init_cpu_ftr_reg(SYS_ID_AA64DFR0_EL1, info->reg_id_aa64dfr0); in init_cpu_features()
1163 init_cpu_ftr_reg(SYS_ID_AA64DFR1_EL1, info->reg_id_aa64dfr1); in init_cpu_features()
1164 init_cpu_ftr_reg(SYS_ID_AA64ISAR0_EL1, info->reg_id_aa64isar0); in init_cpu_features()
1165 init_cpu_ftr_reg(SYS_ID_AA64ISAR1_EL1, info->reg_id_aa64isar1); in init_cpu_features()
1166 init_cpu_ftr_reg(SYS_ID_AA64ISAR2_EL1, info->reg_id_aa64isar2); in init_cpu_features()
1167 init_cpu_ftr_reg(SYS_ID_AA64ISAR3_EL1, info->reg_id_aa64isar3); in init_cpu_features()
1168 init_cpu_ftr_reg(SYS_ID_AA64MMFR0_EL1, info->reg_id_aa64mmfr0); in init_cpu_features()
1169 init_cpu_ftr_reg(SYS_ID_AA64MMFR1_EL1, info->reg_id_aa64mmfr1); in init_cpu_features()
1170 init_cpu_ftr_reg(SYS_ID_AA64MMFR2_EL1, info->reg_id_aa64mmfr2); in init_cpu_features()
1171 init_cpu_ftr_reg(SYS_ID_AA64MMFR3_EL1, info->reg_id_aa64mmfr3); in init_cpu_features()
1172 init_cpu_ftr_reg(SYS_ID_AA64MMFR4_EL1, info->reg_id_aa64mmfr4); in init_cpu_features()
1173 init_cpu_ftr_reg(SYS_ID_AA64PFR0_EL1, info->reg_id_aa64pfr0); in init_cpu_features()
1174 init_cpu_ftr_reg(SYS_ID_AA64PFR1_EL1, info->reg_id_aa64pfr1); in init_cpu_features()
1175 init_cpu_ftr_reg(SYS_ID_AA64PFR2_EL1, info->reg_id_aa64pfr2); in init_cpu_features()
1176 init_cpu_ftr_reg(SYS_ID_AA64ZFR0_EL1, info->reg_id_aa64zfr0); in init_cpu_features()
1177 init_cpu_ftr_reg(SYS_ID_AA64SMFR0_EL1, info->reg_id_aa64smfr0); in init_cpu_features()
1178 init_cpu_ftr_reg(SYS_ID_AA64FPFR0_EL1, info->reg_id_aa64fpfr0); in init_cpu_features()
1180 if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) in init_cpu_features()
1181 init_32bit_cpu_features(&info->aarch32); in init_cpu_features()
1201 if (id_aa64pfr0_mpam(info->reg_id_aa64pfr0)) in init_cpu_features()
1202 init_cpu_ftr_reg(SYS_MPAMIDR_EL1, info->reg_mpamidr); in init_cpu_features()
1204 if (id_aa64pfr1_mte(info->reg_id_aa64pfr1)) in init_cpu_features()
1205 init_cpu_ftr_reg(SYS_GMID_EL1, info->reg_gmid); in init_cpu_features()
1212 for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) { in update_cpu_ftr_reg()
1213 s64 ftr_cur = arm64_ftr_value(ftrp, reg->sys_val); in update_cpu_ftr_reg()
1220 reg->sys_val = arm64_ftr_set_value(ftrp, reg->sys_val, ftr_new); in update_cpu_ftr_reg()
1225 static int check_update_ftr_reg(u32 sys_id, int cpu, u64 val, u64 boot) in check_update_ftr_reg() argument
1233 if ((boot & regp->strict_mask) == (val & regp->strict_mask)) in check_update_ftr_reg()
1235 pr_warn("SANITY CHECK: Unexpected variation in %s. Boot CPU: %#016llx, CPU%d: %#016llx\n", in check_update_ftr_reg()
1236 regp->name, boot, cpu, val); in check_update_ftr_reg()
1248 for (ftrp = regp->ftr_bits; ftrp->width; ftrp++) { in relax_cpu_ftr_reg()
1249 if (ftrp->shift == field) { in relax_cpu_ftr_reg()
1250 regp->strict_mask &= ~arm64_ftr_mask(ftrp); in relax_cpu_ftr_reg()
1256 WARN_ON(!ftrp->width); in relax_cpu_ftr_reg()
1267 if (id_aa64pfr0_32bit_el0(boot->reg_id_aa64pfr0)) in lazy_init_32bit_cpu_features()
1270 boot->aarch32 = info->aarch32; in lazy_init_32bit_cpu_features()
1271 init_32bit_cpu_features(&boot->aarch32); in lazy_init_32bit_cpu_features()
1275 static int update_32bit_cpu_features(int cpu, struct cpuinfo_32bit *info, in update_32bit_cpu_features() argument
1283 * EL1-dependent register fields to avoid spurious sanity check fails. in update_32bit_cpu_features()
1294 taint |= check_update_ftr_reg(SYS_ID_DFR0_EL1, cpu, in update_32bit_cpu_features()
1295 info->reg_id_dfr0, boot->reg_id_dfr0); in update_32bit_cpu_features()
1296 taint |= check_update_ftr_reg(SYS_ID_DFR1_EL1, cpu, in update_32bit_cpu_features()
1297 info->reg_id_dfr1, boot->reg_id_dfr1); in update_32bit_cpu_features()
1298 taint |= check_update_ftr_reg(SYS_ID_ISAR0_EL1, cpu, in update_32bit_cpu_features()
1299 info->reg_id_isar0, boot->reg_id_isar0); in update_32bit_cpu_features()
1300 taint |= check_update_ftr_reg(SYS_ID_ISAR1_EL1, cpu, in update_32bit_cpu_features()
1301 info->reg_id_isar1, boot->reg_id_isar1); in update_32bit_cpu_features()
1302 taint |= check_update_ftr_reg(SYS_ID_ISAR2_EL1, cpu, in update_32bit_cpu_features()
1303 info->reg_id_isar2, boot->reg_id_isar2); in update_32bit_cpu_features()
1304 taint |= check_update_ftr_reg(SYS_ID_ISAR3_EL1, cpu, in update_32bit_cpu_features()
1305 info->reg_id_isar3, boot->reg_id_isar3); in update_32bit_cpu_features()
1306 taint |= check_update_ftr_reg(SYS_ID_ISAR4_EL1, cpu, in update_32bit_cpu_features()
1307 info->reg_id_isar4, boot->reg_id_isar4); in update_32bit_cpu_features()
1308 taint |= check_update_ftr_reg(SYS_ID_ISAR5_EL1, cpu, in update_32bit_cpu_features()
1309 info->reg_id_isar5, boot->reg_id_isar5); in update_32bit_cpu_features()
1310 taint |= check_update_ftr_reg(SYS_ID_ISAR6_EL1, cpu, in update_32bit_cpu_features()
1311 info->reg_id_isar6, boot->reg_id_isar6); in update_32bit_cpu_features()
1318 taint |= check_update_ftr_reg(SYS_ID_MMFR0_EL1, cpu, in update_32bit_cpu_features()
1319 info->reg_id_mmfr0, boot->reg_id_mmfr0); in update_32bit_cpu_features()
1320 taint |= check_update_ftr_reg(SYS_ID_MMFR1_EL1, cpu, in update_32bit_cpu_features()
1321 info->reg_id_mmfr1, boot->reg_id_mmfr1); in update_32bit_cpu_features()
1322 taint |= check_update_ftr_reg(SYS_ID_MMFR2_EL1, cpu, in update_32bit_cpu_features()
1323 info->reg_id_mmfr2, boot->reg_id_mmfr2); in update_32bit_cpu_features()
1324 taint |= check_update_ftr_reg(SYS_ID_MMFR3_EL1, cpu, in update_32bit_cpu_features()
1325 info->reg_id_mmfr3, boot->reg_id_mmfr3); in update_32bit_cpu_features()
1326 taint |= check_update_ftr_reg(SYS_ID_MMFR4_EL1, cpu, in update_32bit_cpu_features()
1327 info->reg_id_mmfr4, boot->reg_id_mmfr4); in update_32bit_cpu_features()
1328 taint |= check_update_ftr_reg(SYS_ID_MMFR5_EL1, cpu, in update_32bit_cpu_features()
1329 info->reg_id_mmfr5, boot->reg_id_mmfr5); in update_32bit_cpu_features()
1330 taint |= check_update_ftr_reg(SYS_ID_PFR0_EL1, cpu, in update_32bit_cpu_features()
1331 info->reg_id_pfr0, boot->reg_id_pfr0); in update_32bit_cpu_features()
1332 taint |= check_update_ftr_reg(SYS_ID_PFR1_EL1, cpu, in update_32bit_cpu_features()
1333 info->reg_id_pfr1, boot->reg_id_pfr1); in update_32bit_cpu_features()
1334 taint |= check_update_ftr_reg(SYS_ID_PFR2_EL1, cpu, in update_32bit_cpu_features()
1335 info->reg_id_pfr2, boot->reg_id_pfr2); in update_32bit_cpu_features()
1336 taint |= check_update_ftr_reg(SYS_MVFR0_EL1, cpu, in update_32bit_cpu_features()
1337 info->reg_mvfr0, boot->reg_mvfr0); in update_32bit_cpu_features()
1338 taint |= check_update_ftr_reg(SYS_MVFR1_EL1, cpu, in update_32bit_cpu_features()
1339 info->reg_mvfr1, boot->reg_mvfr1); in update_32bit_cpu_features()
1340 taint |= check_update_ftr_reg(SYS_MVFR2_EL1, cpu, in update_32bit_cpu_features()
1341 info->reg_mvfr2, boot->reg_mvfr2); in update_32bit_cpu_features()
1347 * Update system wide CPU feature registers with the values from a
1348 * non-boot CPU. Also performs SANITY checks to make sure that there
1349 * aren't any insane variations from that of the boot CPU.
1351 void update_cpu_features(int cpu, in update_cpu_features() argument
1358 * The kernel can handle differing I-cache policies, but otherwise in update_cpu_features()
1362 taint |= check_update_ftr_reg(SYS_CTR_EL0, cpu, in update_cpu_features()
1363 info->reg_ctr, boot->reg_ctr); in update_cpu_features()
1370 taint |= check_update_ftr_reg(SYS_DCZID_EL0, cpu, in update_cpu_features()
1371 info->reg_dczid, boot->reg_dczid); in update_cpu_features()
1374 taint |= check_update_ftr_reg(SYS_CNTFRQ_EL0, cpu, in update_cpu_features()
1375 info->reg_cntfrq, boot->reg_cntfrq); in update_cpu_features()
1378 * The kernel uses self-hosted debug features and expects CPUs to in update_cpu_features()
1383 taint |= check_update_ftr_reg(SYS_ID_AA64DFR0_EL1, cpu, in update_cpu_features()
1384 info->reg_id_aa64dfr0, boot->reg_id_aa64dfr0); in update_cpu_features()
1385 taint |= check_update_ftr_reg(SYS_ID_AA64DFR1_EL1, cpu, in update_cpu_features()
1386 info->reg_id_aa64dfr1, boot->reg_id_aa64dfr1); in update_cpu_features()
1388 * Even in big.LITTLE, processors should be identical instruction-set in update_cpu_features()
1391 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR0_EL1, cpu, in update_cpu_features()
1392 info->reg_id_aa64isar0, boot->reg_id_aa64isar0); in update_cpu_features()
1393 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR1_EL1, cpu, in update_cpu_features()
1394 info->reg_id_aa64isar1, boot->reg_id_aa64isar1); in update_cpu_features()
1395 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR2_EL1, cpu, in update_cpu_features()
1396 info->reg_id_aa64isar2, boot->reg_id_aa64isar2); in update_cpu_features()
1397 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR3_EL1, cpu, in update_cpu_features()
1398 info->reg_id_aa64isar3, boot->reg_id_aa64isar3); in update_cpu_features()
1405 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR0_EL1, cpu, in update_cpu_features()
1406 info->reg_id_aa64mmfr0, boot->reg_id_aa64mmfr0); in update_cpu_features()
1407 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR1_EL1, cpu, in update_cpu_features()
1408 info->reg_id_aa64mmfr1, boot->reg_id_aa64mmfr1); in update_cpu_features()
1409 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR2_EL1, cpu, in update_cpu_features()
1410 info->reg_id_aa64mmfr2, boot->reg_id_aa64mmfr2); in update_cpu_features()
1411 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR3_EL1, cpu, in update_cpu_features()
1412 info->reg_id_aa64mmfr3, boot->reg_id_aa64mmfr3); in update_cpu_features()
1414 taint |= check_update_ftr_reg(SYS_ID_AA64PFR0_EL1, cpu, in update_cpu_features()
1415 info->reg_id_aa64pfr0, boot->reg_id_aa64pfr0); in update_cpu_features()
1416 taint |= check_update_ftr_reg(SYS_ID_AA64PFR1_EL1, cpu, in update_cpu_features()
1417 info->reg_id_aa64pfr1, boot->reg_id_aa64pfr1); in update_cpu_features()
1418 taint |= check_update_ftr_reg(SYS_ID_AA64PFR2_EL1, cpu, in update_cpu_features()
1419 info->reg_id_aa64pfr2, boot->reg_id_aa64pfr2); in update_cpu_features()
1421 taint |= check_update_ftr_reg(SYS_ID_AA64ZFR0_EL1, cpu, in update_cpu_features()
1422 info->reg_id_aa64zfr0, boot->reg_id_aa64zfr0); in update_cpu_features()
1424 taint |= check_update_ftr_reg(SYS_ID_AA64SMFR0_EL1, cpu, in update_cpu_features()
1425 info->reg_id_aa64smfr0, boot->reg_id_aa64smfr0); in update_cpu_features()
1427 taint |= check_update_ftr_reg(SYS_ID_AA64FPFR0_EL1, cpu, in update_cpu_features()
1428 info->reg_id_aa64fpfr0, boot->reg_id_aa64fpfr0); in update_cpu_features()
1453 if (id_aa64pfr0_mpam(info->reg_id_aa64pfr0)) { in update_cpu_features()
1454 taint |= check_update_ftr_reg(SYS_MPAMIDR_EL1, cpu, in update_cpu_features()
1455 info->reg_mpamidr, boot->reg_mpamidr); in update_cpu_features()
1464 id_aa64pfr1_mte(info->reg_id_aa64pfr1)) { in update_cpu_features()
1465 taint |= check_update_ftr_reg(SYS_GMID_EL1, cpu, in update_cpu_features()
1466 info->reg_gmid, boot->reg_gmid); in update_cpu_features()
1477 if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) { in update_cpu_features()
1479 taint |= update_32bit_cpu_features(cpu, &info->aarch32, in update_cpu_features()
1480 &boot->aarch32); in update_cpu_features()
1484 * Mismatched CPU features are a recipe for disaster. Don't even in update_cpu_features()
1488 pr_warn_once("Unsupported CPU feature variation detected.\n"); in update_cpu_features()
1499 return regp->sys_val; in read_sanitised_ftr_reg()
1507 * __read_sysreg_by_encoding() - Used by a STARTING cpu before cpuinfo is populated.
1508 * Read the system register on the current CPU
1567 val &= ~regp->override->mask; in __read_sysreg_by_encoding()
1568 val |= (regp->override->val & regp->override->mask); in __read_sysreg_by_encoding()
1574 #include <linux/irqchip/arm-gic-v3.h>
1588 val = cpuid_feature_extract_field_width(reg, entry->field_pos, in feature_matches()
1589 entry->field_width, in feature_matches()
1590 entry->sign); in feature_matches()
1592 tmp = entry->min_field_value; in feature_matches()
1593 tmp <<= entry->field_pos; in feature_matches()
1595 min = cpuid_feature_extract_field_width(tmp, entry->field_pos, in feature_matches()
1596 entry->field_width, in feature_matches()
1597 entry->sign); in feature_matches()
1599 tmp = entry->max_field_value; in feature_matches()
1600 tmp <<= entry->field_pos; in feature_matches()
1602 max = cpuid_feature_extract_field_width(tmp, entry->field_pos, in feature_matches()
1603 entry->field_width, in feature_matches()
1604 entry->sign); in feature_matches()
1614 return read_sanitised_ftr_reg(entry->sys_reg); in read_scoped_sysreg()
1616 return __read_sysreg_by_encoding(entry->sys_reg); in read_scoped_sysreg()
1626 regp = get_arm64_ftr_reg(entry->sys_reg); in has_user_cpuid_feature()
1630 mask = cpuid_feature_extract_unsigned_field_width(regp->user_mask, in has_user_cpuid_feature()
1631 entry->field_pos, in has_user_cpuid_feature()
1632 entry->field_width); in has_user_cpuid_feature()
1701 pr_info("detected: 32-bit EL0 Support\n"); in has_32bit_el0()
1716 entry->desc); in has_useable_gicv3_cpuif()
1737 * If the CPU exposes raw CTR_EL0.IDC = 0, while effectively in cpu_emulate_effective_ctr()
1739 * to the CTR_EL0 on this CPU and emulate it with the real/safe in cpu_emulate_effective_ctr()
1763 * Kdump isn't guaranteed to power-off all secondary CPUs, CNP in has_useable_cnp()
1764 * may share TLB entries with a CPU stuck in the crashed in has_useable_cnp()
1806 /* Defer to CPU feature registers */ in unmap_kernel_at_el0()
1815 * ThunderX leads to apparent I-cache corruption of kernel text, which in unmap_kernel_at_el0()
1817 * on the cpus_have_*cap() helpers here to detect the CPU erratum in unmap_kernel_at_el0()
1824 __kpti_forced = -1; in unmap_kernel_at_el0()
1837 __kpti_forced = -1; in unmap_kernel_at_el0()
1933 #define KPTI_NG_TEMP_VA (-(1UL << PMD_SHIFT))
1944 kpti_ng_temp_alloc -= PAGE_SIZE; in kpti_ng_pgd_alloc()
1954 int cpu = smp_processor_id(); in __kpti_install_ng_mappings() local
1962 levels = 4; in __kpti_install_ng_mappings()
1963 else if (levels == 4 && !pgtable_l4_enabled()) in __kpti_install_ng_mappings()
1968 if (!cpu) { in __kpti_install_ng_mappings()
1970 kpti_ng_temp_pgd = (pgd_t *)(alloc + (levels - 1) * PAGE_SIZE); in __kpti_install_ng_mappings()
1979 // +--------+-/-------+-/------ +-/------ +-\\\--------+ in __kpti_install_ng_mappings()
1981 // +--------+-\-------+-\------ +-\------ +-///--------+ in __kpti_install_ng_mappings()
1987 // to be used as a ad-hoc fixmap. in __kpti_install_ng_mappings()
1995 remap_fn(cpu, num_online_cpus(), kpti_ng_temp_pgd_pa, KPTI_NG_TEMP_VA); in __kpti_install_ng_mappings()
1998 if (!cpu) { in __kpti_install_ng_mappings()
2013 * We don't need to rewrite the page-tables if either we've done in kpti_install_ng_mappings()
2047 __kpti_forced = enabled ? 1 : -1; in parse_kpti()
2100 * DBM is a non-conflicting feature. i.e, the kernel can safely in has_hw_dbm()
2102 * unconditionally enable the capability to allow any late CPU in has_hw_dbm()
2104 * CPU, if it is supported. in has_hw_dbm()
2115 * The "amu_cpus" cpumask only signals that the CPU implementation for the
2117 * information regarding all the events that it supports. When a CPU bit is
2119 * of the 4 fixed counters for that CPU. But this does not guarantee that the
2125 bool cpu_has_amu_feat(int cpu) in cpu_has_amu_feat() argument
2127 return cpumask_test_cpu(cpu, &amu_cpus); in cpu_has_amu_feat()
2150 * The AMU extension is a non-conflicting feature: the kernel can in has_amu()
2153 * the capability to allow any late CPU to use the feature. in has_amu()
2158 * present on that respective CPU. The enable function will also in has_amu()
2183 * that, freshly-onlined CPUs will set tpidr_el2, so we don't need to in cpu_copy_el2regs()
2197 pr_warn("unavailable: %s\n", cap->desc); in has_nested_virt_support()
2240 * The ptr-auth feature levels are not intercompatible with lower in has_address_auth_cpucap()
2241 * levels. Hence we must match ptr-auth feature level of the secondary in has_address_auth_cpucap()
2242 * CPUs with that of the boot CPU. The level of boot cpu is fetched in has_address_auth_cpucap()
2246 * boot CPU as a mismatched secondary CPU is parked before it gets in has_address_auth_cpucap()
2249 boot_val = cpuid_feature_extract_field(read_sanitised_ftr_reg(entry->sys_reg), in has_address_auth_cpucap()
2250 entry->field_pos, entry->sign); in has_address_auth_cpucap()
2252 return boot_val >= entry->min_field_value; in has_address_auth_cpucap()
2254 sec_val = cpuid_feature_extract_field(__read_sysreg_by_encoding(entry->sys_reg), in has_address_auth_cpucap()
2255 entry->field_pos, entry->sign); in has_address_auth_cpucap()
2256 return (sec_val >= entry->min_field_value) && (sec_val == boot_val); in has_address_auth_cpucap()
2293 * ARM64_HAS_GIC_CPUIF_SYSREGS has a lower index, and is a boot CPU in can_use_gic_priorities()
2312 * ARM64_HAS_GIC_PRIO_MASKING has a lower index, and is a boot CPU in has_gic_prio_relaxed_sync()
2336 * Use of X16/X17 for tail-calls and trampolines that jump to in bti_enable()
2374 regp->user_mask &= ~ID_AA64ISAR1_EL1_BF16_MASK; in user_feature_fixup()
2382 regp->user_mask &= ~ID_AA64PFR1_EL1_SSBS_MASK; in user_feature_fixup()
2432 /* Internal helper functions to match cpu capability type */
2436 return !!(cap->type & ARM64_CPUCAP_OPTIONAL_FOR_LATE_CPU); in cpucap_late_cpu_optional()
2442 return !!(cap->type & ARM64_CPUCAP_PERMITTED_FOR_LATE_CPU); in cpucap_late_cpu_permitted()
2448 return !!(cap->type & ARM64_CPUCAP_PANIC_ON_CONFLICT); in cpucap_panic_on_conflict()
2457 /* Check firmware actually enabled MPAM on this cpu. */ in test_has_mpam()
2466 * which is configured unrestricted. This avoids priority-inversion in cpu_enable_mpam()
2493 .desc = "GIC system register CPU interface",
2573 .desc = "32-bit EL1 Support",
2601 * the CPU doesn't need KPTI. See unmap_kernel_at_el0 for
2674 .desc = "Stage-2 Force Write-Back",
2681 .desc = "ARMv8.4 Translation Table Level",
2873 .desc = "RCpc load-acquire (LDAPR)",
2951 .desc = "Stage-1 Permission Indirection Extension (S1PIE)",
2971 .desc = "52-bit Virtual Addressing for KVM (LPA2)",
2990 .desc = "52-bit Virtual Addressing (LVA)",
2993 .desc = "52-bit Virtual Addressing (LPA2)",
3025 .desc = "Stage-1 Permission Overlay Extension (S1POE)",
3259 * check is future proof, by making sure value is non-zero. in compat_has_neon()
3301 switch (cap->hwcap_type) { in cap_set_elf_hwcap()
3303 cpu_set_feature(cap->hwcap); in cap_set_elf_hwcap()
3307 compat_elf_hwcap |= (u32)cap->hwcap; in cap_set_elf_hwcap()
3310 compat_elf_hwcap2 |= (u32)cap->hwcap; in cap_set_elf_hwcap()
3324 switch (cap->hwcap_type) { in cpus_have_elf_hwcap()
3326 rc = cpu_have_feature(cap->hwcap); in cpus_have_elf_hwcap()
3330 rc = (compat_elf_hwcap & (u32)cap->hwcap) != 0; in cpus_have_elf_hwcap()
3333 rc = (compat_elf_hwcap2 & (u32)cap->hwcap) != 0; in cpus_have_elf_hwcap()
3346 /* We support emulation of accesses to CPU ID feature registers */ in setup_elf_hwcaps()
3348 for (; hwcaps->matches; hwcaps++) in setup_elf_hwcaps()
3349 if (hwcaps->matches(hwcaps, cpucap_default_scope(hwcaps))) in setup_elf_hwcaps()
3361 if (!caps || !(caps->type & scope_mask) || in update_cpu_capabilities()
3362 cpus_have_cap(caps->capability) || in update_cpu_capabilities()
3363 !caps->matches(caps, cpucap_default_scope(caps))) in update_cpu_capabilities()
3366 if (caps->desc && !caps->cpus) in update_cpu_capabilities()
3367 pr_info("detected: %s\n", caps->desc); in update_cpu_capabilities()
3369 __set_bit(caps->capability, system_cpucaps); in update_cpu_capabilities()
3371 if ((scope_mask & SCOPE_BOOT_CPU) && (caps->type & SCOPE_BOOT_CPU)) in update_cpu_capabilities()
3372 set_bit(caps->capability, boot_cpucaps); in update_cpu_capabilities()
3377 * Enable all the available capabilities on this CPU. The capabilities
3391 if (!(cap->type & non_boot_scope)) in cpu_enable_non_boot_scope_capabilities()
3394 if (cap->cpu_enable) in cpu_enable_non_boot_scope_capabilities()
3395 cap->cpu_enable(cap); in cpu_enable_non_boot_scope_capabilities()
3415 if (!caps || !(caps->type & scope_mask) || in enable_cpu_capabilities()
3416 !cpus_have_cap(caps->capability)) in enable_cpu_capabilities()
3419 if (boot_scope && caps->cpu_enable) in enable_cpu_capabilities()
3422 * before any secondary CPU boots. Thus, each secondary in enable_cpu_capabilities()
3425 * the boot CPU, for which the capability must be in enable_cpu_capabilities()
3429 caps->cpu_enable(caps); in enable_cpu_capabilities()
3433 * For all non-boot scope capabilities, use stop_machine() in enable_cpu_capabilities()
3446 * action on this CPU.
3458 if (!caps || !(caps->type & scope_mask)) in verify_local_cpu_caps()
3461 cpu_has_cap = caps->matches(caps, SCOPE_LOCAL_CPU); in verify_local_cpu_caps()
3462 system_has_cap = cpus_have_cap(caps->capability); in verify_local_cpu_caps()
3466 * Check if the new CPU misses an advertised feature, in verify_local_cpu_caps()
3473 * whether the CPU has it or not, as it is enabeld in verify_local_cpu_caps()
3475 * appropriate action on this CPU. in verify_local_cpu_caps()
3477 if (caps->cpu_enable) in verify_local_cpu_caps()
3478 caps->cpu_enable(caps); in verify_local_cpu_caps()
3481 * Check if the CPU has this capability if it isn't in verify_local_cpu_caps()
3490 pr_crit("CPU%d: Detected conflict for capability %d (%s), System: %d, CPU: %d\n", in verify_local_cpu_caps()
3491 smp_processor_id(), caps->capability, in verify_local_cpu_caps()
3492 caps->desc, system_has_cap, cpu_has_cap); in verify_local_cpu_caps()
3502 * Check for CPU features that are used in early boot
3503 * based on the Boot CPU value.
3516 for (; caps->matches; caps++) in __verify_local_elf_hwcaps()
3517 if (cpus_have_elf_hwcap(caps) && !caps->matches(caps, SCOPE_LOCAL_CPU)) { in __verify_local_elf_hwcaps()
3518 pr_crit("CPU%d: missing HWCAP: %s\n", in __verify_local_elf_hwcaps()
3519 smp_processor_id(), caps->desc); in __verify_local_elf_hwcaps()
3537 pr_crit("CPU%d: SVE: vector length support mismatch\n", in verify_sve_features()
3550 pr_crit("CPU%d: SME: vector length support mismatch\n", in verify_sme_features()
3575 pr_crit("CPU%d: VMID width mismatch\n", smp_processor_id()); in verify_hyp_capabilities()
3584 pr_crit("CPU%d: IPA range mismatch\n", smp_processor_id()); in verify_hyp_capabilities()
3597 pr_crit("CPU%d: MPAM version mismatch\n", smp_processor_id()); in verify_mpam_capabilities()
3605 pr_crit("CPU%d: Missing MPAM HCR\n", smp_processor_id()); in verify_mpam_capabilities()
3614 pr_crit("CPU%d: MPAM PARTID/PMG max values are mismatched\n", smp_processor_id()); in verify_mpam_capabilities()
3620 * Run through the enabled system capabilities and enable() it on this CPU.
3622 * Any new CPU should match the system wide status of the capability. If the
3623 * new CPU doesn't have a capability which the system now has enabled, we
3625 * we park the CPU.
3653 * All secondary CPUs should conform to the early CPU features in check_local_cpu_capabilities()
3654 * in use by the kernel based on boot CPU. in check_local_cpu_capabilities()
3659 * If we haven't finalised the system capabilities, this CPU gets in check_local_cpu_capabilities()
3661 * Otherwise, this CPU should verify that it has all the system in check_local_cpu_capabilities()
3676 return cap->matches(cap, SCOPE_LOCAL_CPU); in this_cpu_has_cap()
3685 * - The system wide safe registers are set with all the SMP CPUs and,
3686 * - The SYSTEM_FEATURE system_cpucaps may not have been set.
3694 return cap->matches(cap, SCOPE_SYSTEM); in __system_matches_cap()
3734 * The boot CPU's feature register values have been recorded. Detect in setup_boot_cpu_capabilities()
3735 * boot cpucaps and local cpucaps for the boot CPU, then enable and in setup_boot_cpu_capabilities()
3746 * Initialize the indirect array of CPU capabilities pointers before we in setup_boot_cpu_features()
3747 * handle the boot CPU. in setup_boot_cpu_features()
3752 * Detect broken pseudo-NMI. Must be called _before_ the call to in setup_boot_cpu_features()
3764 * The system-wide safe feature register values have been finalized. in setup_system_capabilities()
3779 if (caps && caps->cpus && caps->desc && in setup_system_capabilities()
3780 cpumask_any(caps->cpus) < nr_cpu_ids) in setup_system_capabilities()
3781 pr_info("detected: %s on CPU%*pbl\n", in setup_system_capabilities()
3782 caps->desc, cpumask_pr_args(caps->cpus)); in setup_system_capabilities()
3823 static int enable_mismatched_32bit_el0(unsigned int cpu) in enable_mismatched_32bit_el0() argument
3826 * The first 32-bit-capable CPU we detected and so can no longer in enable_mismatched_32bit_el0()
3827 * be offlined by userspace. -1 indicates we haven't yet onlined in enable_mismatched_32bit_el0()
3828 * a 32-bit-capable CPU. in enable_mismatched_32bit_el0()
3830 static int lucky_winner = -1; in enable_mismatched_32bit_el0()
3832 struct cpuinfo_arm64 *info = &per_cpu(cpu_data, cpu); in enable_mismatched_32bit_el0()
3835 if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) { in enable_mismatched_32bit_el0()
3836 if (!housekeeping_cpu(cpu, HK_TYPE_TICK)) in enable_mismatched_32bit_el0()
3837 pr_info("Treating adaptive-ticks CPU %u as 64-bit only\n", cpu); in enable_mismatched_32bit_el0()
3843 cpumask_set_cpu(cpu, cpu_32bit_el0_mask); in enable_mismatched_32bit_el0()
3855 * 32-bit EL0 online so that is_cpu_allowed() doesn't end up rejecting in enable_mismatched_32bit_el0()
3856 * every CPU in the system for a 32-bit task. in enable_mismatched_32bit_el0()
3858 lucky_winner = cpu_32bit ? cpu : cpumask_any_and(cpu_32bit_el0_mask, in enable_mismatched_32bit_el0()
3860 get_cpu_device(lucky_winner)->offline_disabled = true; in enable_mismatched_32bit_el0()
3863 pr_info("Asymmetric 32-bit EL0 support detected on CPU %u; CPU hot-unplug disabled on CPU %u\n", in enable_mismatched_32bit_el0()
3864 cpu, lucky_winner); in enable_mismatched_32bit_el0()
3874 return -ENOMEM; in init_32bit_el0_mask()
3889 * Op0 = 0x3, CRn = 0x0, Op1 = 0x0, CRm = [0, 2 - 7]
3890 * See Table C5-6 System instruction encodings for System register accesses,
3920 return -EINVAL; in emulate_id_reg()
3931 return -EINVAL; in emulate_sys_reg()