arm64/kernel/cpu_errata.c

1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <linux/arm-smccc.h>
35 		return midr_is_cpu_model_range(read_cpuid_id(), range->model,  in is_midr_in_range()
36 					       range->rv_min, range->rv_max);  in is_midr_in_range()
40 					    range->model,  in is_midr_in_range()
41 					    range->rv_min, range->rv_max))  in is_midr_in_range()
49 	while (ranges->model)  in is_midr_in_range_list()
61 	if (!is_midr_in_range(&entry->midr_range))  in __is_affected_midr_range()
65 	for (fix = entry->fixed_revs; fix && fix->revidr_mask; fix++)  in __is_affected_midr_range()
66 		if (midr == fix->midr_rv && (revidr & fix->revidr_mask))  in __is_affected_midr_range()
95 	return is_midr_in_range_list(entry->midr_range_list);  in is_affected_midr_range_list()
109 	return model == entry->midr_range.model;  in is_kryo_midr()
156 	if (cap->capability == ARM64_WORKAROUND_1542419)  in cpu_enable_trap_ctr_access()
314 		/* Cortex-A510 r0p0 -> r1p1. Fixed in r1p2 */
339 	/* Cavium ThunderX, T88 pass 1.x - 2.1 */
349 	/* Cavium ThunderX, T88 pass 1.x - 2.2 */
351 	/* Cavium ThunderX, T81 pass 1.0 - 1.2 */
377 	/* Cortex-A53 r0p[012]: ARM errata 826319, 827319, 824069 */
381 	/* Cortex-A53 r0p[01] : ARM errata 819472 */
390  * - 1188873 affects r0p0 to r2p0
391  * - 1418040 affects r0p0 to r3p1
394 	/* Cortex-A76 r0p0 to r3p1 */
396 	/* Neoverse-N1 r0p0 to r3p1 */
406 	/* Cortex-A53 r0p[01234] */
408 	/* Brahma-B53 r0p[0] */
419 		/* Cortex-A53 r0p[01234] */
425 		/* Brahma-B53 r0p[0] */
436 	/* Cortex A76 r0p0 to r2p0 */
444 	/* Cortex A55 r0p0 to r2p0 */
455 	/* Cortex-A76 r0p0 - r3p1 */
518 	/* Cortex-A520 r0p0 to r0p1 */
571 	/* Cortex-A57 r0p0 - r1p2 */
581 	/* Cortex-A57 r0p0 - r1p2 */
654 	/* Cortex-A73 all versions */
661 		.desc = "Spectre-v2",
669 	/* Must come after the Spectre-v2 entry */
670 		.desc = "Spectre-v3a",
678 		.desc = "Spectre-v4",
685 		.desc = "Spectre-BHB",
698 		 * also need the non-affected CPUs to be able to come
765 		 * driver and can be applied per-cpu. So, we can allow
808 		/* Cortex-A510 r0p0 - r0p2 */
818 		/* Cortex-A510 r0p0-r1p1 */
827 		/* Cortex-A510 r0p0 - r0p2 */
836 		/* Cortex-A510 r0p0 - r0p1 */
852 		/* Cortex-A510 r0p0 - r1p1 */
859 		.desc = "SSBS not fully self-synchronizing",
868 		/* Cortex-A520 r0p0 - r0p1 */