Lines Matching +full:3 +full:- +full:7
1 /* SPDX-License-Identifier: GPL-2.0-only */
14 #include <linux/kasan-tags.h>
16 #include <asm/gpr-num.h>
22 * [20-19] : Op0
23 * [18-16] : Op1
24 * [15-12] : CRn
25 * [11-8] : CRm
26 * [7-5] : Op2
83 * As per Arm ARM for v8-A, Section "C.5.1.3 op0 == 0b00, architectural hints,
96 #define PSTATE_UAO pstate_field(0, 3)
97 #define PSTATE_SSBS pstate_field(3, 1)
98 #define PSTATE_DIT pstate_field(3, 2)
99 #define PSTATE_TCO pstate_field(3, 4)
112 /* Register-based PAN access, for save/restore purposes */
113 #define SYS_PSTATE_PAN sys_reg(3, 0, 4, 2, 3)
116 __emit_inst(0xd5000000 | sys_insn(0, 3, 3, (CRm), (op2)) | ((Rt) & 0x1f))
118 #define SB_BARRIER_INSN __SYS_BARRIER_INSN(0, 7, 31)
120 #define SYS_DC_ISW sys_insn(1, 0, 7, 6, 2)
121 #define SYS_DC_IGSW sys_insn(1, 0, 7, 6, 4)
122 #define SYS_DC_IGDSW sys_insn(1, 0, 7, 6, 6)
123 #define SYS_DC_CSW sys_insn(1, 0, 7, 10, 2)
124 #define SYS_DC_CGSW sys_insn(1, 0, 7, 10, 4)
125 #define SYS_DC_CGDSW sys_insn(1, 0, 7, 10, 6)
126 #define SYS_DC_CISW sys_insn(1, 0, 7, 14, 2)
127 #define SYS_DC_CIGSW sys_insn(1, 0, 7, 14, 4)
128 #define SYS_DC_CIGDSW sys_insn(1, 0, 7, 14, 6)
130 #define SYS_IC_IALLUIS sys_insn(1, 0, 7, 1, 0)
131 #define SYS_IC_IALLU sys_insn(1, 0, 7, 5, 0)
132 #define SYS_IC_IVAU sys_insn(1, 3, 7, 5, 1)
134 #define SYS_DC_IVAC sys_insn(1, 0, 7, 6, 1)
135 #define SYS_DC_IGVAC sys_insn(1, 0, 7, 6, 3)
136 #define SYS_DC_IGDVAC sys_insn(1, 0, 7, 6, 5)
138 #define SYS_DC_CVAC sys_insn(1, 3, 7, 10, 1)
139 #define SYS_DC_CGVAC sys_insn(1, 3, 7, 10, 3)
140 #define SYS_DC_CGDVAC sys_insn(1, 3, 7, 10, 5)
142 #define SYS_DC_CVAU sys_insn(1, 3, 7, 11, 1)
144 #define SYS_DC_CVAP sys_insn(1, 3, 7, 12, 1)
145 #define SYS_DC_CGVAP sys_insn(1, 3, 7, 12, 3)
146 #define SYS_DC_CGDVAP sys_insn(1, 3, 7, 12, 5)
148 #define SYS_DC_CVADP sys_insn(1, 3, 7, 13, 1)
149 #define SYS_DC_CGVADP sys_insn(1, 3, 7, 13, 3)
150 #define SYS_DC_CGDVADP sys_insn(1, 3, 7, 13, 5)
152 #define SYS_DC_CIVAC sys_insn(1, 3, 7, 14, 1)
153 #define SYS_DC_CIGVAC sys_insn(1, 3, 7, 14, 3)
154 #define SYS_DC_CIGDVAC sys_insn(1, 3, 7, 14, 5)
157 #define SYS_DC_ZVA sys_insn(1, 3, 7, 4, 1)
158 #define SYS_DC_GVA sys_insn(1, 3, 7, 4, 3)
159 #define SYS_DC_GZVA sys_insn(1, 3, 7, 4, 4)
167 #include "asm/sysreg-defs.h"
173 #define SYS_SVCR_SMSTOP_SM_EL0 sys_reg(0, 3, 4, 2, 3)
174 #define SYS_SVCR_SMSTART_SM_EL0 sys_reg(0, 3, 4, 3, 3)
175 #define SYS_SVCR_SMSTOP_SMZA_EL0 sys_reg(0, 3, 4, 6, 3)
180 #define SYS_DBGWCRn_EL1(n) sys_reg(2, 0, 0, n, 7)
184 #define OSLSR_EL1_OSLM_MASK (BIT(3) | BIT(0))
186 #define OSLSR_EL1_OSLM_IMPLEMENTED BIT(3)
189 #define SYS_OSDLR_EL1 sys_reg(2, 0, 1, 3, 4)
191 #define SYS_DBGCLAIMSET_EL1 sys_reg(2, 0, 7, 8, 6)
192 #define SYS_DBGCLAIMCLR_EL1 sys_reg(2, 0, 7, 9, 6)
193 #define SYS_DBGAUTHSTATUS_EL1 sys_reg(2, 0, 7, 14, 6)
194 #define SYS_MDCCSR_EL0 sys_reg(2, 3, 0, 1, 0)
195 #define SYS_DBGDTR_EL0 sys_reg(2, 3, 0, 4, 0)
196 #define SYS_DBGDTRRX_EL0 sys_reg(2, 3, 0, 5, 0)
197 #define SYS_DBGDTRTX_EL0 sys_reg(2, 3, 0, 5, 0)
198 #define SYS_DBGVCR32_EL2 sys_reg(2, 4, 0, 7, 0)
212 #define SYS_TRCITECR_EL1 sys_reg(3, 0, 1, 2, 3)
213 #define SYS_TRCACATR(m) sys_reg(2, 1, 2, ((m & 7) << 1), (2 | (m >> 3)))
214 #define SYS_TRCACVR(m) sys_reg(2, 1, 2, ((m & 7) << 1), (0 | (m >> 3)))
215 #define SYS_TRCAUTHSTATUS sys_reg(2, 1, 7, 14, 6)
219 #define SYS_TRCCIDCCTLR0 sys_reg(2, 1, 3, 0, 2)
220 #define SYS_TRCCIDCCTLR1 sys_reg(2, 1, 3, 1, 2)
221 #define SYS_TRCCIDCVR(m) sys_reg(2, 1, 3, ((m & 7) << 1), 0)
222 #define SYS_TRCCLAIMCLR sys_reg(2, 1, 7, 9, 6)
223 #define SYS_TRCCLAIMSET sys_reg(2, 1, 7, 8, 6)
224 #define SYS_TRCCNTCTLR(m) sys_reg(2, 1, 0, (4 | (m & 3)), 5)
225 #define SYS_TRCCNTRLDVR(m) sys_reg(2, 1, 0, (0 | (m & 3)), 5)
226 #define SYS_TRCCNTVR(m) sys_reg(2, 1, 0, (8 | (m & 3)), 5)
228 #define SYS_TRCDEVARCH sys_reg(2, 1, 7, 15, 6)
229 #define SYS_TRCDEVID sys_reg(2, 1, 7, 2, 7)
232 #define SYS_TRCEXTINSELR(m) sys_reg(2, 1, 0, (8 | (m & 3)), 4)
233 #define SYS_TRCIDR0 sys_reg(2, 1, 0, 8, 7)
235 #define SYS_TRCIDR11 sys_reg(2, 1, 0, 3, 6)
238 #define SYS_TRCIDR1 sys_reg(2, 1, 0, 9, 7)
239 #define SYS_TRCIDR2 sys_reg(2, 1, 0, 10, 7)
240 #define SYS_TRCIDR3 sys_reg(2, 1, 0, 11, 7)
241 #define SYS_TRCIDR4 sys_reg(2, 1, 0, 12, 7)
242 #define SYS_TRCIDR5 sys_reg(2, 1, 0, 13, 7)
243 #define SYS_TRCIDR6 sys_reg(2, 1, 0, 14, 7)
244 #define SYS_TRCIDR7 sys_reg(2, 1, 0, 15, 7)
247 #define SYS_TRCIMSPEC(m) sys_reg(2, 1, 0, (m & 7), 7)
254 #define SYS_TRCSEQEVR(m) sys_reg(2, 1, 0, (m & 3), 4)
256 #define SYS_TRCSEQSTR sys_reg(2, 1, 0, 7, 4)
257 #define SYS_TRCSSCCR(m) sys_reg(2, 1, 1, (m & 7), 2)
258 #define SYS_TRCSSCSR(m) sys_reg(2, 1, 1, (8 | (m & 7)), 2)
259 #define SYS_TRCSSPCICR(m) sys_reg(2, 1, 1, (m & 7), 3)
261 #define SYS_TRCSTATR sys_reg(2, 1, 0, 3, 0)
267 #define SYS_TRCVIPCSSCTLR sys_reg(2, 1, 0, 3, 2)
269 #define SYS_TRCVMIDCCTLR0 sys_reg(2, 1, 3, 2, 2)
270 #define SYS_TRCVMIDCCTLR1 sys_reg(2, 1, 3, 3, 2)
271 #define SYS_TRCVMIDCVR(m) sys_reg(2, 1, 3, ((m & 7) << 1), 1)
278 #define SYS_MIDR_EL1 sys_reg(3, 0, 0, 0, 0)
279 #define SYS_MPIDR_EL1 sys_reg(3, 0, 0, 0, 5)
280 #define SYS_REVIDR_EL1 sys_reg(3, 0, 0, 0, 6)
282 #define SYS_ACTLR_EL1 sys_reg(3, 0, 1, 0, 1)
283 #define SYS_RGSR_EL1 sys_reg(3, 0, 1, 0, 5)
284 #define SYS_GCR_EL1 sys_reg(3, 0, 1, 0, 6)
286 #define SYS_TCR_EL1 sys_reg(3, 0, 2, 0, 2)
288 #define SYS_APIAKEYLO_EL1 sys_reg(3, 0, 2, 1, 0)
289 #define SYS_APIAKEYHI_EL1 sys_reg(3, 0, 2, 1, 1)
290 #define SYS_APIBKEYLO_EL1 sys_reg(3, 0, 2, 1, 2)
291 #define SYS_APIBKEYHI_EL1 sys_reg(3, 0, 2, 1, 3)
293 #define SYS_APDAKEYLO_EL1 sys_reg(3, 0, 2, 2, 0)
294 #define SYS_APDAKEYHI_EL1 sys_reg(3, 0, 2, 2, 1)
295 #define SYS_APDBKEYLO_EL1 sys_reg(3, 0, 2, 2, 2)
296 #define SYS_APDBKEYHI_EL1 sys_reg(3, 0, 2, 2, 3)
298 #define SYS_APGAKEYLO_EL1 sys_reg(3, 0, 2, 3, 0)
299 #define SYS_APGAKEYHI_EL1 sys_reg(3, 0, 2, 3, 1)
301 #define SYS_SPSR_EL1 sys_reg(3, 0, 4, 0, 0)
302 #define SYS_ELR_EL1 sys_reg(3, 0, 4, 0, 1)
304 #define SYS_ICC_PMR_EL1 sys_reg(3, 0, 4, 6, 0)
306 #define SYS_AFSR0_EL1 sys_reg(3, 0, 5, 1, 0)
307 #define SYS_AFSR1_EL1 sys_reg(3, 0, 5, 1, 1)
308 #define SYS_ESR_EL1 sys_reg(3, 0, 5, 2, 0)
310 #define SYS_ERRIDR_EL1 sys_reg(3, 0, 5, 3, 0)
311 #define SYS_ERRSELR_EL1 sys_reg(3, 0, 5, 3, 1)
312 #define SYS_ERXFR_EL1 sys_reg(3, 0, 5, 4, 0)
313 #define SYS_ERXCTLR_EL1 sys_reg(3, 0, 5, 4, 1)
314 #define SYS_ERXSTATUS_EL1 sys_reg(3, 0, 5, 4, 2)
315 #define SYS_ERXADDR_EL1 sys_reg(3, 0, 5, 4, 3)
316 #define SYS_ERXPFGF_EL1 sys_reg(3, 0, 5, 4, 4)
317 #define SYS_ERXPFGCTL_EL1 sys_reg(3, 0, 5, 4, 5)
318 #define SYS_ERXPFGCDN_EL1 sys_reg(3, 0, 5, 4, 6)
319 #define SYS_ERXMISC0_EL1 sys_reg(3, 0, 5, 5, 0)
320 #define SYS_ERXMISC1_EL1 sys_reg(3, 0, 5, 5, 1)
321 #define SYS_ERXMISC2_EL1 sys_reg(3, 0, 5, 5, 2)
322 #define SYS_ERXMISC3_EL1 sys_reg(3, 0, 5, 5, 3)
323 #define SYS_TFSR_EL1 sys_reg(3, 0, 5, 6, 0)
324 #define SYS_TFSRE0_EL1 sys_reg(3, 0, 5, 6, 1)
326 #define SYS_PAR_EL1 sys_reg(3, 0, 7, 4, 0)
338 #define SYS_PAR_EL1_F1_RES0 (BIT(7) | BIT(10) | GENMASK_ULL(47, 16))
341 #define SYS_PAR_EL1_SH GENMASK_ULL(8, 7)
372 #define SYS_PMINTENSET_EL1 sys_reg(3, 0, 9, 14, 1)
373 #define SYS_PMINTENCLR_EL1 sys_reg(3, 0, 9, 14, 2)
375 #define SYS_PMMIR_EL1 sys_reg(3, 0, 9, 14, 6)
377 #define SYS_MAIR_EL1 sys_reg(3, 0, 10, 2, 0)
378 #define SYS_AMAIR_EL1 sys_reg(3, 0, 10, 3, 0)
380 #define SYS_VBAR_EL1 sys_reg(3, 0, 12, 0, 0)
381 #define SYS_DISR_EL1 sys_reg(3, 0, 12, 1, 1)
383 #define SYS_ICC_IAR0_EL1 sys_reg(3, 0, 12, 8, 0)
384 #define SYS_ICC_EOIR0_EL1 sys_reg(3, 0, 12, 8, 1)
385 #define SYS_ICC_HPPIR0_EL1 sys_reg(3, 0, 12, 8, 2)
386 #define SYS_ICC_BPR0_EL1 sys_reg(3, 0, 12, 8, 3)
387 #define SYS_ICC_AP0Rn_EL1(n) sys_reg(3, 0, 12, 8, 4 | n)
391 #define SYS_ICC_AP0R3_EL1 SYS_ICC_AP0Rn_EL1(3)
392 #define SYS_ICC_AP1Rn_EL1(n) sys_reg(3, 0, 12, 9, n)
396 #define SYS_ICC_AP1R3_EL1 SYS_ICC_AP1Rn_EL1(3)
397 #define SYS_ICC_DIR_EL1 sys_reg(3, 0, 12, 11, 1)
398 #define SYS_ICC_RPR_EL1 sys_reg(3, 0, 12, 11, 3)
399 #define SYS_ICC_SGI1R_EL1 sys_reg(3, 0, 12, 11, 5)
400 #define SYS_ICC_ASGI1R_EL1 sys_reg(3, 0, 12, 11, 6)
401 #define SYS_ICC_SGI0R_EL1 sys_reg(3, 0, 12, 11, 7)
402 #define SYS_ICC_IAR1_EL1 sys_reg(3, 0, 12, 12, 0)
403 #define SYS_ICC_EOIR1_EL1 sys_reg(3, 0, 12, 12, 1)
404 #define SYS_ICC_HPPIR1_EL1 sys_reg(3, 0, 12, 12, 2)
405 #define SYS_ICC_BPR1_EL1 sys_reg(3, 0, 12, 12, 3)
406 #define SYS_ICC_CTLR_EL1 sys_reg(3, 0, 12, 12, 4)
407 #define SYS_ICC_SRE_EL1 sys_reg(3, 0, 12, 12, 5)
408 #define SYS_ICC_IGRPEN0_EL1 sys_reg(3, 0, 12, 12, 6)
409 #define SYS_ICC_IGRPEN1_EL1 sys_reg(3, 0, 12, 12, 7)
411 #define SYS_ACCDATA_EL1 sys_reg(3, 0, 13, 0, 5)
413 #define SYS_CNTKCTL_EL1 sys_reg(3, 0, 14, 1, 0)
415 #define SYS_AIDR_EL1 sys_reg(3, 1, 0, 0, 7)
417 #define SYS_RNDR_EL0 sys_reg(3, 3, 2, 4, 0)
418 #define SYS_RNDRRS_EL0 sys_reg(3, 3, 2, 4, 1)
420 #define SYS_PMCR_EL0 sys_reg(3, 3, 9, 12, 0)
421 #define SYS_PMCNTENSET_EL0 sys_reg(3, 3, 9, 12, 1)
422 #define SYS_PMCNTENCLR_EL0 sys_reg(3, 3, 9, 12, 2)
423 #define SYS_PMOVSCLR_EL0 sys_reg(3, 3, 9, 12, 3)
424 #define SYS_PMSWINC_EL0 sys_reg(3, 3, 9, 12, 4)
425 #define SYS_PMCEID0_EL0 sys_reg(3, 3, 9, 12, 6)
426 #define SYS_PMCEID1_EL0 sys_reg(3, 3, 9, 12, 7)
427 #define SYS_PMCCNTR_EL0 sys_reg(3, 3, 9, 13, 0)
428 #define SYS_PMXEVTYPER_EL0 sys_reg(3, 3, 9, 13, 1)
429 #define SYS_PMXEVCNTR_EL0 sys_reg(3, 3, 9, 13, 2)
430 #define SYS_PMUSERENR_EL0 sys_reg(3, 3, 9, 14, 0)
431 #define SYS_PMOVSSET_EL0 sys_reg(3, 3, 9, 14, 3)
433 #define SYS_TPIDR_EL0 sys_reg(3, 3, 13, 0, 2)
434 #define SYS_TPIDRRO_EL0 sys_reg(3, 3, 13, 0, 3)
435 #define SYS_TPIDR2_EL0 sys_reg(3, 3, 13, 0, 5)
437 #define SYS_SCXTNUM_EL0 sys_reg(3, 3, 13, 0, 7)
440 #define SYS_AM_EL0(crm, op2) sys_reg(3, 3, 13, (crm), (op2))
444 #define SYS_AMUSERENR_EL0 SYS_AM_EL0(2, 3)
447 #define SYS_AMCNTENCLR1_EL0 SYS_AM_EL0(3, 0)
448 #define SYS_AMCNTENSET1_EL0 SYS_AM_EL0(3, 1)
453 * Counter: 11 011 1101 010:n<3> n<2:0>
454 * Type: 11 011 1101 011:n<3> n<2:0>
455 * n: 0-15
459 * Counter: 11 011 1101 110:n<3> n<2:0>
460 * Type: 11 011 1101 111:n<3> n<2:0>
461 * n: 0-15
464 #define SYS_AMEVCNTR0_EL0(n) SYS_AM_EL0(4 + ((n) >> 3), (n) & 7)
465 #define SYS_AMEVTYPER0_EL0(n) SYS_AM_EL0(6 + ((n) >> 3), (n) & 7)
466 #define SYS_AMEVCNTR1_EL0(n) SYS_AM_EL0(12 + ((n) >> 3), (n) & 7)
467 #define SYS_AMEVTYPER1_EL0(n) SYS_AM_EL0(14 + ((n) >> 3), (n) & 7)
473 #define SYS_AMEVCNTR0_MEM_STALL SYS_AMEVCNTR0_EL0(3)
475 #define SYS_CNTFRQ_EL0 sys_reg(3, 3, 14, 0, 0)
477 #define SYS_CNTPCT_EL0 sys_reg(3, 3, 14, 0, 1)
478 #define SYS_CNTVCT_EL0 sys_reg(3, 3, 14, 0, 2)
479 #define SYS_CNTPCTSS_EL0 sys_reg(3, 3, 14, 0, 5)
480 #define SYS_CNTVCTSS_EL0 sys_reg(3, 3, 14, 0, 6)
482 #define SYS_CNTP_TVAL_EL0 sys_reg(3, 3, 14, 2, 0)
483 #define SYS_CNTP_CTL_EL0 sys_reg(3, 3, 14, 2, 1)
484 #define SYS_CNTP_CVAL_EL0 sys_reg(3, 3, 14, 2, 2)
486 #define SYS_CNTV_TVAL_EL0 sys_reg(3, 3, 14, 3, 0)
487 #define SYS_CNTV_CTL_EL0 sys_reg(3, 3, 14, 3, 1)
488 #define SYS_CNTV_CVAL_EL0 sys_reg(3, 3, 14, 3, 2)
499 #define __CNTR_CRm(n) (0x8 | (((n) >> 3) & 0x3))
500 #define SYS_PMEVCNTRn_EL0(n) sys_reg(3, 3, 14, __CNTR_CRm(n), __PMEV_op2(n))
501 #define __TYPER_CRm(n) (0xc | (((n) >> 3) & 0x3))
502 #define SYS_PMEVTYPERn_EL0(n) sys_reg(3, 3, 14, __TYPER_CRm(n), __PMEV_op2(n))
504 #define SYS_PMCCFILTR_EL0 sys_reg(3, 3, 14, 15, 7)
506 #define SYS_VPIDR_EL2 sys_reg(3, 4, 0, 0, 0)
507 #define SYS_VMPIDR_EL2 sys_reg(3, 4, 0, 0, 5)
509 #define SYS_SCTLR_EL2 sys_reg(3, 4, 1, 0, 0)
510 #define SYS_ACTLR_EL2 sys_reg(3, 4, 1, 0, 1)
511 #define SYS_SCTLR2_EL2 sys_reg(3, 4, 1, 0, 3)
512 #define SYS_HCR_EL2 sys_reg(3, 4, 1, 1, 0)
513 #define SYS_MDCR_EL2 sys_reg(3, 4, 1, 1, 1)
514 #define SYS_CPTR_EL2 sys_reg(3, 4, 1, 1, 2)
515 #define SYS_HSTR_EL2 sys_reg(3, 4, 1, 1, 3)
516 #define SYS_HACR_EL2 sys_reg(3, 4, 1, 1, 7)
518 #define SYS_TTBR0_EL2 sys_reg(3, 4, 2, 0, 0)
519 #define SYS_TTBR1_EL2 sys_reg(3, 4, 2, 0, 1)
520 #define SYS_TCR_EL2 sys_reg(3, 4, 2, 0, 2)
521 #define SYS_VTTBR_EL2 sys_reg(3, 4, 2, 1, 0)
522 #define SYS_VTCR_EL2 sys_reg(3, 4, 2, 1, 2)
524 #define SYS_VNCR_EL2 sys_reg(3, 4, 2, 2, 0)
525 #define SYS_HAFGRTR_EL2 sys_reg(3, 4, 3, 1, 6)
526 #define SYS_SPSR_EL2 sys_reg(3, 4, 4, 0, 0)
527 #define SYS_ELR_EL2 sys_reg(3, 4, 4, 0, 1)
528 #define SYS_SP_EL1 sys_reg(3, 4, 4, 1, 0)
529 #define SYS_SPSR_irq sys_reg(3, 4, 4, 3, 0)
530 #define SYS_SPSR_abt sys_reg(3, 4, 4, 3, 1)
531 #define SYS_SPSR_und sys_reg(3, 4, 4, 3, 2)
532 #define SYS_SPSR_fiq sys_reg(3, 4, 4, 3, 3)
533 #define SYS_IFSR32_EL2 sys_reg(3, 4, 5, 0, 1)
534 #define SYS_AFSR0_EL2 sys_reg(3, 4, 5, 1, 0)
535 #define SYS_AFSR1_EL2 sys_reg(3, 4, 5, 1, 1)
536 #define SYS_ESR_EL2 sys_reg(3, 4, 5, 2, 0)
537 #define SYS_VSESR_EL2 sys_reg(3, 4, 5, 2, 3)
538 #define SYS_FPEXC32_EL2 sys_reg(3, 4, 5, 3, 0)
539 #define SYS_TFSR_EL2 sys_reg(3, 4, 5, 6, 0)
541 #define SYS_FAR_EL2 sys_reg(3, 4, 6, 0, 0)
542 #define SYS_HPFAR_EL2 sys_reg(3, 4, 6, 0, 4)
544 #define SYS_MAIR_EL2 sys_reg(3, 4, 10, 2, 0)
545 #define SYS_AMAIR_EL2 sys_reg(3, 4, 10, 3, 0)
547 #define SYS_VBAR_EL2 sys_reg(3, 4, 12, 0, 0)
548 #define SYS_RVBAR_EL2 sys_reg(3, 4, 12, 0, 1)
549 #define SYS_RMR_EL2 sys_reg(3, 4, 12, 0, 2)
550 #define SYS_VDISR_EL2 sys_reg(3, 4, 12, 1, 1)
551 #define __SYS__AP0Rx_EL2(x) sys_reg(3, 4, 12, 8, x)
555 #define SYS_ICH_AP0R3_EL2 __SYS__AP0Rx_EL2(3)
557 #define __SYS__AP1Rx_EL2(x) sys_reg(3, 4, 12, 9, x)
561 #define SYS_ICH_AP1R3_EL2 __SYS__AP1Rx_EL2(3)
563 #define SYS_ICH_VSEIR_EL2 sys_reg(3, 4, 12, 9, 4)
564 #define SYS_ICC_SRE_EL2 sys_reg(3, 4, 12, 9, 5)
565 #define SYS_ICH_EISR_EL2 sys_reg(3, 4, 12, 11, 3)
566 #define SYS_ICH_ELRSR_EL2 sys_reg(3, 4, 12, 11, 5)
567 #define SYS_ICH_VMCR_EL2 sys_reg(3, 4, 12, 11, 7)
569 #define __SYS__LR0_EL2(x) sys_reg(3, 4, 12, 12, x)
573 #define SYS_ICH_LR3_EL2 __SYS__LR0_EL2(3)
577 #define SYS_ICH_LR7_EL2 __SYS__LR0_EL2(7)
579 #define __SYS__LR8_EL2(x) sys_reg(3, 4, 12, 13, x)
583 #define SYS_ICH_LR11_EL2 __SYS__LR8_EL2(3)
587 #define SYS_ICH_LR15_EL2 __SYS__LR8_EL2(7)
589 #define SYS_CONTEXTIDR_EL2 sys_reg(3, 4, 13, 0, 1)
590 #define SYS_TPIDR_EL2 sys_reg(3, 4, 13, 0, 2)
591 #define SYS_SCXTNUM_EL2 sys_reg(3, 4, 13, 0, 7)
594 #define __AMEV_CRm(n, m) (n | ((m & 0x8) >> 3))
595 #define __SYS__AMEVCNTVOFF0n_EL2(m) sys_reg(3, 4, 13, __AMEV_CRm(0x8, m), __AMEV_op2(m))
597 #define __SYS__AMEVCNTVOFF1n_EL2(m) sys_reg(3, 4, 13, __AMEV_CRm(0xA, m), __AMEV_op2(m))
600 #define SYS_CNTVOFF_EL2 sys_reg(3, 4, 14, 0, 3)
601 #define SYS_CNTHCTL_EL2 sys_reg(3, 4, 14, 1, 0)
602 #define SYS_CNTHP_TVAL_EL2 sys_reg(3, 4, 14, 2, 0)
603 #define SYS_CNTHP_CTL_EL2 sys_reg(3, 4, 14, 2, 1)
604 #define SYS_CNTHP_CVAL_EL2 sys_reg(3, 4, 14, 2, 2)
605 #define SYS_CNTHV_TVAL_EL2 sys_reg(3, 4, 14, 3, 0)
606 #define SYS_CNTHV_CTL_EL2 sys_reg(3, 4, 14, 3, 1)
607 #define SYS_CNTHV_CVAL_EL2 sys_reg(3, 4, 14, 3, 2)
611 #define SYS_SCTLR_EL12 sys_reg(3, 5, 1, 0, 0)
612 #define SYS_CPACR_EL12 sys_reg(3, 5, 1, 0, 2)
613 #define SYS_SCTLR2_EL12 sys_reg(3, 5, 1, 0, 3)
614 #define SYS_ZCR_EL12 sys_reg(3, 5, 1, 2, 0)
615 #define SYS_TRFCR_EL12 sys_reg(3, 5, 1, 2, 1)
616 #define SYS_SMCR_EL12 sys_reg(3, 5, 1, 2, 6)
617 #define SYS_TTBR0_EL12 sys_reg(3, 5, 2, 0, 0)
618 #define SYS_TTBR1_EL12 sys_reg(3, 5, 2, 0, 1)
619 #define SYS_TCR_EL12 sys_reg(3, 5, 2, 0, 2)
620 #define SYS_TCR2_EL12 sys_reg(3, 5, 2, 0, 3)
621 #define SYS_SPSR_EL12 sys_reg(3, 5, 4, 0, 0)
622 #define SYS_ELR_EL12 sys_reg(3, 5, 4, 0, 1)
623 #define SYS_AFSR0_EL12 sys_reg(3, 5, 5, 1, 0)
624 #define SYS_AFSR1_EL12 sys_reg(3, 5, 5, 1, 1)
625 #define SYS_ESR_EL12 sys_reg(3, 5, 5, 2, 0)
626 #define SYS_TFSR_EL12 sys_reg(3, 5, 5, 6, 0)
627 #define SYS_FAR_EL12 sys_reg(3, 5, 6, 0, 0)
628 #define SYS_PMSCR_EL12 sys_reg(3, 5, 9, 9, 0)
629 #define SYS_MAIR_EL12 sys_reg(3, 5, 10, 2, 0)
630 #define SYS_AMAIR_EL12 sys_reg(3, 5, 10, 3, 0)
631 #define SYS_VBAR_EL12 sys_reg(3, 5, 12, 0, 0)
632 #define SYS_CONTEXTIDR_EL12 sys_reg(3, 5, 13, 0, 1)
633 #define SYS_SCXTNUM_EL12 sys_reg(3, 5, 13, 0, 7)
634 #define SYS_CNTKCTL_EL12 sys_reg(3, 5, 14, 1, 0)
635 #define SYS_CNTP_TVAL_EL02 sys_reg(3, 5, 14, 2, 0)
636 #define SYS_CNTP_CTL_EL02 sys_reg(3, 5, 14, 2, 1)
637 #define SYS_CNTP_CVAL_EL02 sys_reg(3, 5, 14, 2, 2)
638 #define SYS_CNTV_TVAL_EL02 sys_reg(3, 5, 14, 3, 0)
639 #define SYS_CNTV_CTL_EL02 sys_reg(3, 5, 14, 3, 1)
640 #define SYS_CNTV_CVAL_EL02 sys_reg(3, 5, 14, 3, 2)
642 #define SYS_SP_EL2 sys_reg(3, 6, 4, 1, 0)
646 #define AT_CRn 7
651 #define OP_AT_S1E0W sys_insn(AT_Op0, 0, AT_CRn, 8, 3)
660 #define OP_AT_S12E0W sys_insn(AT_Op0, 4, AT_CRn, 8, 7)
672 #define TLBI_CRm_IPAIS 0 /* S2 Inner-Shareable */
673 #define TLBI_CRm_nROS 1 /* non-Range, Outer-Sharable */
674 #define TLBI_CRm_RIS 2 /* Range, Inner-Sharable */
675 #define TLBI_CRm_nRIS 3 /* non-Range, Inner-Sharable */
676 #define TLBI_CRm_IPAONS 4 /* S2 Outer and Non-Shareable */
677 #define TLBI_CRm_ROS 5 /* Range, Outer-Sharable */
678 #define TLBI_CRm_RNS 6 /* Range, Non-Sharable */
679 #define TLBI_CRm_nRNS 7 /* non-Range, Non-Sharable */
684 #define OP_TLBI_VAAE1OS sys_insn(1, 0, 8, 1, 3)
686 #define OP_TLBI_VAALE1OS sys_insn(1, 0, 8, 1, 7)
688 #define OP_TLBI_RVAAE1IS sys_insn(1, 0, 8, 2, 3)
690 #define OP_TLBI_RVAALE1IS sys_insn(1, 0, 8, 2, 7)
691 #define OP_TLBI_VMALLE1IS sys_insn(1, 0, 8, 3, 0)
692 #define OP_TLBI_VAE1IS sys_insn(1, 0, 8, 3, 1)
693 #define OP_TLBI_ASIDE1IS sys_insn(1, 0, 8, 3, 2)
694 #define OP_TLBI_VAAE1IS sys_insn(1, 0, 8, 3, 3)
695 #define OP_TLBI_VALE1IS sys_insn(1, 0, 8, 3, 5)
696 #define OP_TLBI_VAALE1IS sys_insn(1, 0, 8, 3, 7)
698 #define OP_TLBI_RVAAE1OS sys_insn(1, 0, 8, 5, 3)
700 #define OP_TLBI_RVAALE1OS sys_insn(1, 0, 8, 5, 7)
702 #define OP_TLBI_RVAAE1 sys_insn(1, 0, 8, 6, 3)
704 #define OP_TLBI_RVAALE1 sys_insn(1, 0, 8, 6, 7)
705 #define OP_TLBI_VMALLE1 sys_insn(1, 0, 8, 7, 0)
706 #define OP_TLBI_VAE1 sys_insn(1, 0, 8, 7, 1)
707 #define OP_TLBI_ASIDE1 sys_insn(1, 0, 8, 7, 2)
708 #define OP_TLBI_VAAE1 sys_insn(1, 0, 8, 7, 3)
709 #define OP_TLBI_VALE1 sys_insn(1, 0, 8, 7, 5)
710 #define OP_TLBI_VAALE1 sys_insn(1, 0, 8, 7, 7)
714 #define OP_TLBI_VAAE1OSNXS sys_insn(1, 0, 9, 1, 3)
716 #define OP_TLBI_VAALE1OSNXS sys_insn(1, 0, 9, 1, 7)
718 #define OP_TLBI_RVAAE1ISNXS sys_insn(1, 0, 9, 2, 3)
720 #define OP_TLBI_RVAALE1ISNXS sys_insn(1, 0, 9, 2, 7)
721 #define OP_TLBI_VMALLE1ISNXS sys_insn(1, 0, 9, 3, 0)
722 #define OP_TLBI_VAE1ISNXS sys_insn(1, 0, 9, 3, 1)
723 #define OP_TLBI_ASIDE1ISNXS sys_insn(1, 0, 9, 3, 2)
724 #define OP_TLBI_VAAE1ISNXS sys_insn(1, 0, 9, 3, 3)
725 #define OP_TLBI_VALE1ISNXS sys_insn(1, 0, 9, 3, 5)
726 #define OP_TLBI_VAALE1ISNXS sys_insn(1, 0, 9, 3, 7)
728 #define OP_TLBI_RVAAE1OSNXS sys_insn(1, 0, 9, 5, 3)
730 #define OP_TLBI_RVAALE1OSNXS sys_insn(1, 0, 9, 5, 7)
732 #define OP_TLBI_RVAAE1NXS sys_insn(1, 0, 9, 6, 3)
734 #define OP_TLBI_RVAALE1NXS sys_insn(1, 0, 9, 6, 7)
735 #define OP_TLBI_VMALLE1NXS sys_insn(1, 0, 9, 7, 0)
736 #define OP_TLBI_VAE1NXS sys_insn(1, 0, 9, 7, 1)
737 #define OP_TLBI_ASIDE1NXS sys_insn(1, 0, 9, 7, 2)
738 #define OP_TLBI_VAAE1NXS sys_insn(1, 0, 9, 7, 3)
739 #define OP_TLBI_VALE1NXS sys_insn(1, 0, 9, 7, 5)
740 #define OP_TLBI_VAALE1NXS sys_insn(1, 0, 9, 7, 7)
752 #define OP_TLBI_ALLE2IS sys_insn(1, 4, 8, 3, 0)
753 #define OP_TLBI_VAE2IS sys_insn(1, 4, 8, 3, 1)
754 #define OP_TLBI_ALLE1IS sys_insn(1, 4, 8, 3, 4)
755 #define OP_TLBI_VALE2IS sys_insn(1, 4, 8, 3, 5)
756 #define OP_TLBI_VMALLS12E1IS sys_insn(1, 4, 8, 3, 6)
760 #define OP_TLBI_RIPAS2E1OS sys_insn(1, 4, 8, 4, 3)
764 #define OP_TLBI_RIPAS2LE1OS sys_insn(1, 4, 8, 4, 7)
769 #define OP_TLBI_ALLE2 sys_insn(1, 4, 8, 7, 0)
770 #define OP_TLBI_VAE2 sys_insn(1, 4, 8, 7, 1)
771 #define OP_TLBI_ALLE1 sys_insn(1, 4, 8, 7, 4)
772 #define OP_TLBI_VALE2 sys_insn(1, 4, 8, 7, 5)
773 #define OP_TLBI_VMALLS12E1 sys_insn(1, 4, 8, 7, 6)
785 #define OP_TLBI_ALLE2ISNXS sys_insn(1, 4, 9, 3, 0)
786 #define OP_TLBI_VAE2ISNXS sys_insn(1, 4, 9, 3, 1)
787 #define OP_TLBI_ALLE1ISNXS sys_insn(1, 4, 9, 3, 4)
788 #define OP_TLBI_VALE2ISNXS sys_insn(1, 4, 9, 3, 5)
789 #define OP_TLBI_VMALLS12E1ISNXS sys_insn(1, 4, 9, 3, 6)
793 #define OP_TLBI_RIPAS2E1OSNXS sys_insn(1, 4, 9, 4, 3)
797 #define OP_TLBI_RIPAS2LE1OSNXS sys_insn(1, 4, 9, 4, 7)
802 #define OP_TLBI_ALLE2NXS sys_insn(1, 4, 9, 7, 0)
803 #define OP_TLBI_VAE2NXS sys_insn(1, 4, 9, 7, 1)
804 #define OP_TLBI_ALLE1NXS sys_insn(1, 4, 9, 7, 4)
805 #define OP_TLBI_VALE2NXS sys_insn(1, 4, 9, 7, 5)
806 #define OP_TLBI_VMALLS12E1NXS sys_insn(1, 4, 9, 7, 6)
809 #define OP_GCSPUSHX sys_insn(1, 0, 7, 7, 4)
810 #define OP_GCSPOPCX sys_insn(1, 0, 7, 7, 5)
811 #define OP_GCSPOPX sys_insn(1, 0, 7, 7, 6)
812 #define OP_GCSPUSHM sys_insn(1, 3, 7, 7, 0)
814 #define OP_BRB_IALL sys_insn(1, 1, 7, 2, 4)
815 #define OP_BRB_INJ sys_insn(1, 1, 7, 2, 5)
816 #define OP_CFP_RCTX sys_insn(1, 3, 7, 3, 4)
817 #define OP_DVP_RCTX sys_insn(1, 3, 7, 3, 5)
818 #define OP_COSP_RCTX sys_insn(1, 3, 7, 3, 6)
819 #define OP_CPP_RCTX sys_insn(1, 3, 7, 3, 7)
843 #define SCTLR_ELx_SA (BIT(3))
958 * only uses tags in the range 0xF0-0xFF, which we map to MTE tags 0x0-0xF.
986 #define ICH_LR_VIRTUAL_ID_MASK ((1ULL << 32) - 1)
991 #define ICH_LR_STATE (3ULL << 62)
1002 #define ICH_VMCR_FIQ_EN_SHIFT 3
1009 #define ICH_VMCR_BPR1_MASK (7 << ICH_VMCR_BPR1_SHIFT)
1011 #define ICH_VMCR_BPR0_MASK (7 << ICH_VMCR_BPR0_SHIFT)
1172 * set mask are set. Other bits are left as-is.