Lines Matching +full:0487 +full:a
89 * AMO: Override CPSR.A and enable signaling with VA
93 * PTW: Take a stage2 fault if a stage1 walk steps in device memory
151 * 40 bits wide (T0SZ = 24). Systems with a PARange smaller than 40 bits are
167 * See D.10.2.121, VTCR_EL2, in ARM DDI 0487C.a
185 * Where TGRAN_SL0_BASE is a magic number depending on the page size:
222 * descriptors in section D4.2.8 in ARM DDI 0487C.a.
227 * algorithm determines the alignment of a table base address at a given
231 * depending on the T0SZ, the value of "x" is defined based on a
232 * Magic constant for a given PAGE_SIZE and Entry Level. The
254 * We have a magic formula for the Magic_N below:
281 * levels for a given IPA size (which we do, see stage2_pt_levels())
317 * RES0 and polarity masks as of DDI0487J.a, to be updated as needed.
319 * the published ARM ARM, which we use as a reference.
321 * Once we get to a point where the two describe the same thing, we'll
329 * The HFGWTR bits are a subset of HFGRTR bits. To ensure we don't miss any