Lines Matching +full:mi +full:- +full:v

1 /* SPDX-License-Identifier: GPL-2.0 */
22  * two-step process  only requires 1 finite field reduction for every 8
58 MI	.req	v21  label
65 	.arch	armv8-a+crypto
72  * Computes the product of two 128-bit polynomials in X and Y and XORs the
73  * components of the 256-bit product into LO, MI, HI.
81  *  MI += (X_0 + X_1) * (Y_0 + Y_1)
84  * Later, the 256-bit result can be extracted as:
105 	eor	MI.16b, MI.16b, v27.16b
111  * Same as karatsuba1, except overwrites HI, LO, MI rather than XORing into
123 	pmull	MI.1q, v25.1d, v26.1d
129  * Computes the 256-bit polynomial represented by LO, HI, MI. Stores
136 	eor	v4.16b, HI.16b, MI.16b
154  * Computes the 128-bit reduction of PH : PL. Stores the result in dest.
159  * We have a 256-bit polynomial PH : PL = P_3 : P_2 : P_1 : P_0 that is the
160  * product of two 128-bit polynomials in Montgomery form.  We need to reduce it
173  * x^64 * g*(x) * P_0 + P_0, where g*(x) is bits 64-127 of g(x).  Adding this to
175  * = T_1 : T_0 = g*(x) * P_0.  Thus, bits 0-63 got "folded" into bits 64-191.
177  * Repeating this same process on the next 64 bits "folds" bits 64-127 into bits
178  * 128-255, giving the answer in bits 128-255. This time, we need to cancel P_1
179  * + T_0 in bits 64-127. The multiple of g(x) required is (P_1 + T_0) * g(x) *
181  * P_2 + P_0 + T_1 + V_0 : 0 : 0, where V = V_1 : V_0 = g*(x) * (P_1 + T_0).
185  *   V = V_1 : V_0 = g*(x) * (P_1 + T_0)
190  * T_1 into dest.  This allows us to reuse P_1 + T_0 when computing V.
220 	eor		MI.16b, MI.16b, MI.16b
305  * Computes op1*op2*x^{-128} mod x^128 + x^127 + x^126 + x^121 + 1
325  *	h^n * accumulator + h^n * m_0 + ... + h^1 * m_{n-1}
328  * x0 - pointer to precomputed key powers h^8 ... h^1
329  * x1 - pointer to message blocks
330  * x2 - number of blocks to hash
331  * x3 - pointer to accumulator