Lines Matching +full:parkmode +full:- +full:disable +full:- +full:hs +full:- +full:quirk
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/rockchip,rk3576-cru.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/phy/phy.h>
10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/power/rockchip,rk3576-power.h>
12 #include <dt-bindings/reset/rockchip,rk3576-cru.h>
13 #include <dt-bindings/soc/rockchip,boot-mode.h>
18 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <2>;
52 xin32k: clock-xin32k {
53 compatible = "fixed-clock";
54 clock-frequency = <32768>;
55 clock-output-names = "xin32k";
56 #clock-cells = <0>;
59 xin24m: clock-xin24m {
60 compatible = "fixed-clock";
61 #clock-cells = <0>;
62 clock-frequency = <24000000>;
63 clock-output-names = "xin24m";
66 spll: clock-spll {
67 compatible = "fixed-clock";
68 #clock-cells = <0>;
69 clock-frequency = <702000000>;
70 clock-output-names = "spll";
74 #address-cells = <1>;
75 #size-cells = <0>;
77 cpu-map {
110 compatible = "arm,cortex-a53";
112 enable-method = "psci";
113 capacity-dmips-mhz = <485>;
115 operating-points-v2 = <&cluster0_opp_table>;
116 #cooling-cells = <2>;
117 dynamic-power-coefficient = <120>;
118 cpu-idle-states = <&CPU_SLEEP>;
123 compatible = "arm,cortex-a53";
125 enable-method = "psci";
126 capacity-dmips-mhz = <485>;
128 operating-points-v2 = <&cluster0_opp_table>;
129 cpu-idle-states = <&CPU_SLEEP>;
134 compatible = "arm,cortex-a53";
136 enable-method = "psci";
137 capacity-dmips-mhz = <485>;
139 operating-points-v2 = <&cluster0_opp_table>;
140 cpu-idle-states = <&CPU_SLEEP>;
145 compatible = "arm,cortex-a53";
147 enable-method = "psci";
148 capacity-dmips-mhz = <485>;
150 operating-points-v2 = <&cluster0_opp_table>;
151 cpu-idle-states = <&CPU_SLEEP>;
156 compatible = "arm,cortex-a72";
158 enable-method = "psci";
159 capacity-dmips-mhz = <1024>;
161 operating-points-v2 = <&cluster1_opp_table>;
162 #cooling-cells = <2>;
163 dynamic-power-coefficient = <320>;
164 cpu-idle-states = <&CPU_SLEEP>;
169 compatible = "arm,cortex-a72";
171 enable-method = "psci";
172 capacity-dmips-mhz = <1024>;
174 operating-points-v2 = <&cluster1_opp_table>;
175 cpu-idle-states = <&CPU_SLEEP>;
180 compatible = "arm,cortex-a72";
182 enable-method = "psci";
183 capacity-dmips-mhz = <1024>;
185 operating-points-v2 = <&cluster1_opp_table>;
186 cpu-idle-states = <&CPU_SLEEP>;
191 compatible = "arm,cortex-a72";
193 enable-method = "psci";
194 capacity-dmips-mhz = <1024>;
196 operating-points-v2 = <&cluster1_opp_table>;
197 cpu-idle-states = <&CPU_SLEEP>;
200 idle-states {
201 entry-method = "psci";
203 CPU_SLEEP: cpu-sleep {
204 compatible = "arm,idle-state";
205 arm,psci-suspend-param = <0x0010000>;
206 entry-latency-us = <120>;
207 exit-latency-us = <250>;
208 min-residency-us = <900>;
209 local-timer-stop;
214 cluster0_opp_table: opp-table-cluster0 {
215 compatible = "operating-points-v2";
216 opp-shared;
218 opp-408000000 {
219 opp-hz = /bits/ 64 <408000000>;
220 opp-microvolt = <700000 700000 950000>;
221 clock-latency-ns = <40000>;
224 opp-600000000 {
225 opp-hz = /bits/ 64 <600000000>;
226 opp-microvolt = <700000 700000 950000>;
227 clock-latency-ns = <40000>;
230 opp-816000000 {
231 opp-hz = /bits/ 64 <816000000>;
232 opp-microvolt = <700000 700000 950000>;
233 clock-latency-ns = <40000>;
236 opp-1008000000 {
237 opp-hz = /bits/ 64 <1008000000>;
238 opp-microvolt = <700000 700000 950000>;
239 clock-latency-ns = <40000>;
242 opp-1200000000 {
243 opp-hz = /bits/ 64 <1200000000>;
244 opp-microvolt = <700000 700000 950000>;
245 clock-latency-ns = <40000>;
248 opp-1416000000 {
249 opp-hz = /bits/ 64 <1416000000>;
250 opp-microvolt = <725000 725000 950000>;
251 clock-latency-ns = <40000>;
254 opp-1608000000 {
255 opp-hz = /bits/ 64 <1608000000>;
256 opp-microvolt = <750000 750000 950000>;
257 clock-latency-ns = <40000>;
260 opp-1800000000 {
261 opp-hz = /bits/ 64 <1800000000>;
262 opp-microvolt = <825000 825000 950000>;
263 clock-latency-ns = <40000>;
264 opp-suspend;
267 opp-2016000000 {
268 opp-hz = /bits/ 64 <2016000000>;
269 opp-microvolt = <900000 900000 950000>;
270 clock-latency-ns = <40000>;
273 opp-2208000000 {
274 opp-hz = /bits/ 64 <2208000000>;
275 opp-microvolt = <950000 950000 950000>;
276 clock-latency-ns = <40000>;
280 cluster1_opp_table: opp-table-cluster1 {
281 compatible = "operating-points-v2";
282 opp-shared;
284 opp-408000000 {
285 opp-hz = /bits/ 64 <408000000>;
286 opp-microvolt = <700000 700000 950000>;
287 clock-latency-ns = <40000>;
288 opp-suspend;
291 opp-600000000 {
292 opp-hz = /bits/ 64 <600000000>;
293 opp-microvolt = <700000 700000 950000>;
294 clock-latency-ns = <40000>;
297 opp-816000000 {
298 opp-hz = /bits/ 64 <816000000>;
299 opp-microvolt = <700000 700000 950000>;
300 clock-latency-ns = <40000>;
303 opp-1008000000 {
304 opp-hz = /bits/ 64 <1008000000>;
305 opp-microvolt = <700000 700000 950000>;
306 clock-latency-ns = <40000>;
309 opp-1200000000 {
310 opp-hz = /bits/ 64 <1200000000>;
311 opp-microvolt = <700000 700000 950000>;
312 clock-latency-ns = <40000>;
315 opp-1416000000 {
316 opp-hz = /bits/ 64 <1416000000>;
317 opp-microvolt = <712500 712500 950000>;
318 clock-latency-ns = <40000>;
321 opp-1608000000 {
322 opp-hz = /bits/ 64 <1608000000>;
323 opp-microvolt = <737500 737500 950000>;
324 clock-latency-ns = <40000>;
327 opp-1800000000 {
328 opp-hz = /bits/ 64 <1800000000>;
329 opp-microvolt = <800000 800000 950000>;
330 clock-latency-ns = <40000>;
333 opp-2016000000 {
334 opp-hz = /bits/ 64 <2016000000>;
335 opp-microvolt = <862500 862500 950000>;
336 clock-latency-ns = <40000>;
339 opp-2208000000 {
340 opp-hz = /bits/ 64 <2208000000>;
341 opp-microvolt = <925000 925000 950000>;
342 clock-latency-ns = <40000>;
345 opp-2304000000 {
346 opp-hz = /bits/ 64 <2304000000>;
347 opp-microvolt = <950000 950000 950000>;
348 clock-latency-ns = <40000>;
352 gpu_opp_table: opp-table-gpu {
353 compatible = "operating-points-v2";
355 opp-300000000 {
356 opp-hz = /bits/ 64 <300000000>;
357 opp-microvolt = <700000 700000 850000>;
360 opp-400000000 {
361 opp-hz = /bits/ 64 <400000000>;
362 opp-microvolt = <700000 700000 850000>;
365 opp-500000000 {
366 opp-hz = /bits/ 64 <500000000>;
367 opp-microvolt = <700000 700000 850000>;
370 opp-600000000 {
371 opp-hz = /bits/ 64 <600000000>;
372 opp-microvolt = <700000 700000 850000>;
375 opp-700000000 {
376 opp-hz = /bits/ 64 <700000000>;
377 opp-microvolt = <725000 725000 850000>;
380 opp-800000000 {
381 opp-hz = /bits/ 64 <800000000>;
382 opp-microvolt = <775000 775000 850000>;
385 opp-900000000 {
386 opp-hz = /bits/ 64 <900000000>;
387 opp-microvolt = <825000 825000 850000>;
390 opp-950000000 {
391 opp-hz = /bits/ 64 <950000000>;
392 opp-microvolt = <850000 850000 850000>;
396 display_subsystem: display-subsystem {
397 compatible = "rockchip,display-subsystem";
403 compatible = "arm,scmi-smc";
404 arm,smc-id = <0x82000010>;
406 #address-cells = <1>;
407 #size-cells = <0>;
411 #clock-cells = <1>;
416 pmu_a53: pmu-a53 {
417 compatible = "arm,cortex-a53-pmu";
422 interrupt-affinity = <&cpu_l0>, <&cpu_l1>, <&cpu_l2>, <&cpu_l3>;
425 pmu_a72: pmu-a72 {
426 compatible = "arm,cortex-a72-pmu";
431 interrupt-affinity = <&cpu_b0>, <&cpu_b1>, <&cpu_b2>, <&cpu_b3>;
435 compatible = "arm,psci-1.0";
440 compatible = "arm,armv8-timer";
448 compatible = "simple-bus";
449 #address-cells = <2>;
450 #size-cells = <2>;
454 compatible = "rockchip,rk3576-dwc3", "snps,dwc3";
459 clock-names = "ref_clk", "suspend_clk", "bus_clk";
461 power-domains = <&power RK3576_PD_USB>;
465 phy-names = "usb2-phy", "usb3-phy";
468 snps,dis-u1-entry-quirk;
469 snps,dis-u2-entry-quirk;
470 snps,dis-u2-freeclk-exists-quirk;
471 snps,dis-del-phy-power-chg-quirk;
472 snps,dis-tx-ipgap-linecheck-quirk;
473 snps,parkmode-disable-hs-quirk;
474 snps,parkmode-disable-ss-quirk;
479 compatible = "rockchip,rk3576-dwc3", "snps,dwc3";
484 clock-names = "ref_clk", "suspend_clk", "bus_clk";
486 power-domains = <&power RK3576_PD_PHP>;
490 phy-names = "usb2-phy", "usb3-phy";
493 snps,dis-u1-entry-quirk;
494 snps,dis-u2-entry-quirk;
495 snps,dis-u2-freeclk-exists-quirk;
496 snps,dis-del-phy-power-chg-quirk;
497 snps,dis-tx-ipgap-linecheck-quirk;
499 snps,parkmode-disable-hs-quirk;
500 snps,parkmode-disable-ss-quirk;
501 dma-coherent;
506 compatible = "rockchip,rk3576-sys-grf", "syscon";
511 compatible = "rockchip,rk3576-bigcore-grf", "syscon";
516 compatible = "rockchip,rk3576-litcore-grf", "syscon";
521 compatible = "rockchip,rk3576-cci-grf", "syscon";
526 compatible = "rockchip,rk3576-gpu-grf", "syscon";
531 compatible = "rockchip,rk3576-npu-grf", "syscon";
536 compatible = "rockchip,rk3576-vo0-grf", "syscon";
541 compatible = "rockchip,rk3576-usb-grf", "syscon";
546 compatible = "rockchip,rk3576-php-grf", "syscon";
551 compatible = "rockchip,rk3576-pmu0-grf", "syscon", "simple-mfd";
556 compatible = "rockchip,rk3576-pmu1-grf", "syscon";
561 compatible = "rockchip,rk3576-pipe-phy-grf", "syscon";
566 compatible = "rockchip,rk3576-pipe-phy-grf", "syscon";
571 compatible = "rockchip,rk3576-usbdpphy-grf", "syscon";
576 compatible = "rockchip,rk3576-usb2phy-grf", "syscon", "simple-mfd";
578 #address-cells = <1>;
579 #size-cells = <1>;
581 u2phy0: usb2-phy@0 {
582 compatible = "rockchip,rk3576-usb2phy";
585 reset-names = "phy", "apb";
589 clock-names = "phyclk", "aclk", "aclk_slv";
590 clock-output-names = "usb480m_phy0";
591 #clock-cells = <0>;
594 u2phy0_otg: otg-port {
595 #phy-cells = <0>;
599 interrupt-names = "otg-bvalid", "otg-id", "linestate";
604 u2phy1: usb2-phy@2000 {
605 compatible = "rockchip,rk3576-usb2phy";
608 reset-names = "phy", "apb";
612 clock-names = "phyclk", "aclk", "aclk_slv";
613 clock-output-names = "usb480m_phy1";
614 #clock-cells = <0>;
617 u2phy1_otg: otg-port {
618 #phy-cells = <0>;
622 interrupt-names = "otg-bvalid", "otg-id", "linestate";
629 compatible = "rockchip,rk3576-hdptxphy-grf", "syscon";
634 compatible = "rockchip,rk3576-vo1-grf", "syscon";
640 compatible = "rockchip,rk3576-sdgmac-grf", "syscon";
645 compatible = "rockchip,rk3576-ioc-grf", "syscon", "simple-mfd";
649 cru: clock-controller@27200000 {
650 compatible = "rockchip,rk3576-cru";
652 #clock-cells = <1>;
653 #reset-cells = <1>;
655 assigned-clocks =
664 assigned-clock-parents = <&cru PLL_AUPLL>;
665 assigned-clock-rates =
677 compatible = "rockchip,rk3576-i2c", "rockchip,rk3399-i2c";
680 clock-names = "i2c", "pclk";
682 pinctrl-names = "default";
683 pinctrl-0 = <&i2c0m0_xfer>;
684 #address-cells = <1>;
685 #size-cells = <0>;
690 compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart";
692 reg-shift = <2>;
693 reg-io-width = <4>;
695 clock-names = "baudclk", "apb_pclk";
698 pinctrl-names = "default";
699 pinctrl-0 = <&uart1m0_xfer>;
703 pmu: power-management@27380000 {
704 compatible = "rockchip,rk3576-pmu", "syscon", "simple-mfd";
707 power: power-controller {
708 compatible = "rockchip,rk3576-power-controller";
709 #power-domain-cells = <1>;
710 #address-cells = <1>;
711 #size-cells = <0>;
713 power-domain@RK3576_PD_NPU {
715 #power-domain-cells = <1>;
716 #address-cells = <1>;
717 #size-cells = <0>;
719 power-domain@RK3576_PD_NPUTOP {
734 #power-domain-cells = <1>;
735 #address-cells = <1>;
736 #size-cells = <0>;
738 power-domain@RK3576_PD_NPU0 {
743 #power-domain-cells = <0>;
745 power-domain@RK3576_PD_NPU1 {
750 #power-domain-cells = <0>;
755 power-domain@RK3576_PD_GPU {
759 #power-domain-cells = <0>;
762 power-domain@RK3576_PD_NVM {
767 #power-domain-cells = <1>;
768 #address-cells = <1>;
769 #size-cells = <0>;
771 power-domain@RK3576_PD_SDGMAC {
788 #power-domain-cells = <0>;
792 power-domain@RK3576_PD_PHP {
800 #power-domain-cells = <1>;
801 #address-cells = <1>;
802 #size-cells = <0>;
804 power-domain@RK3576_PD_SUBPHP {
806 #power-domain-cells = <0>;
810 power-domain@RK3576_PD_AUDIO {
812 #power-domain-cells = <0>;
815 power-domain@RK3576_PD_VEPU1 {
820 #power-domain-cells = <0>;
823 power-domain@RK3576_PD_VPU {
840 #power-domain-cells = <0>;
843 power-domain@RK3576_PD_VDEC {
848 #power-domain-cells = <0>;
851 power-domain@RK3576_PD_VI {
870 #power-domain-cells = <1>;
871 #address-cells = <1>;
872 #size-cells = <0>;
874 power-domain@RK3576_PD_VEPU0 {
879 #power-domain-cells = <0>;
883 power-domain@RK3576_PD_VOP {
891 #power-domain-cells = <1>;
892 #address-cells = <1>;
893 #size-cells = <0>;
895 power-domain@RK3576_PD_USB {
904 #power-domain-cells = <0>;
907 power-domain@RK3576_PD_VO0 {
915 #power-domain-cells = <0>;
918 power-domain@RK3576_PD_VO1 {
926 #power-domain-cells = <0>;
933 compatible = "rockchip,rk3576-mali", "arm,mali-bifrost";
935 assigned-clocks = <&scmi_clk SCMI_CLK_GPU>;
936 assigned-clock-rates = <198000000>;
938 clock-names = "core";
939 dynamic-power-coefficient = <1625>;
943 interrupt-names = "job", "mmu", "gpu";
944 operating-points-v2 = <&gpu_opp_table>;
945 power-domains = <&power RK3576_PD_GPU>;
946 #cooling-cells = <2>;
951 compatible = "rockchip,rk3576-vop";
953 reg-names = "vop", "gamma-lut";
958 interrupt-names = "sys",
967 clock-names = "aclk",
973 power-domains = <&power RK3576_PD_VOP>;
979 #address-cells = <1>;
980 #size-cells = <0>;
983 #address-cells = <1>;
984 #size-cells = <0>;
989 #address-cells = <1>;
990 #size-cells = <0>;
995 #address-cells = <1>;
996 #size-cells = <0>;
1003 compatible = "rockchip,rk3576-iommu", "rockchip,rk3568-iommu";
1007 clock-names = "aclk", "iface";
1008 #iommu-cells = <0>;
1009 power-domains = <&power RK3576_PD_VOP>;
1014 compatible = "rockchip,rk3576-dw-hdmi-qp";
1022 clock-names = "pclk", "earc", "ref", "aud", "hdp", "hclk_vo1";
1028 interrupt-names = "avp", "cec", "earc", "main", "hpd";
1030 pinctrl-names = "default";
1031 pinctrl-0 = <&hdmi_txm0_pins &hdmi_tx_scl &hdmi_tx_sda>;
1032 power-domains = <&power RK3576_PD_VO0>;
1034 reset-names = "ref", "hdp";
1036 rockchip,vo-grf = <&vo0_grf>;
1040 #address-cells = <1>;
1041 #size-cells = <0>;
1054 compatible = "rockchip,rk3576-qos", "syscon";
1059 compatible = "rockchip,rk3576-qos", "syscon";
1064 compatible = "rockchip,rk3576-qos", "syscon";
1069 compatible = "rockchip,rk3576-qos", "syscon";
1074 compatible = "rockchip,rk3576-qos", "syscon";
1079 compatible = "rockchip,rk3576-qos", "syscon";
1084 compatible = "rockchip,rk3576-qos", "syscon";
1089 compatible = "rockchip,rk3576-qos", "syscon";
1094 compatible = "rockchip,rk3576-qos", "syscon";
1099 compatible = "rockchip,rk3576-qos", "syscon";
1104 compatible = "rockchip,rk3576-qos", "syscon";
1109 compatible = "rockchip,rk3576-qos", "syscon";
1114 compatible = "rockchip,rk3576-qos", "syscon";
1119 compatible = "rockchip,rk3576-qos", "syscon";
1124 compatible = "rockchip,rk3576-qos", "syscon";
1129 compatible = "rockchip,rk3576-qos", "syscon";
1134 compatible = "rockchip,rk3576-qos", "syscon";
1139 compatible = "rockchip,rk3576-qos", "syscon";
1144 compatible = "rockchip,rk3576-qos", "syscon";
1149 compatible = "rockchip,rk3576-qos", "syscon";
1154 compatible = "rockchip,rk3576-qos", "syscon";
1159 compatible = "rockchip,rk3576-qos", "syscon";
1164 compatible = "rockchip,rk3576-qos", "syscon";
1169 compatible = "rockchip,rk3576-qos", "syscon";
1174 compatible = "rockchip,rk3576-qos", "syscon";
1179 compatible = "rockchip,rk3576-qos", "syscon";
1184 compatible = "rockchip,rk3576-qos", "syscon";
1189 compatible = "rockchip,rk3576-qos", "syscon";
1194 compatible = "rockchip,rk3576-qos", "syscon";
1199 compatible = "rockchip,rk3576-qos", "syscon";
1204 compatible = "rockchip,rk3576-qos", "syscon";
1209 compatible = "rockchip,rk3576-qos", "syscon";
1214 compatible = "rockchip,rk3576-qos", "syscon";
1219 compatible = "rockchip,rk3576-qos", "syscon";
1224 compatible = "rockchip,rk3576-qos", "syscon";
1229 compatible = "rockchip,rk3576-qos", "syscon";
1234 compatible = "rockchip,rk3576-qos", "syscon";
1239 compatible = "rockchip,rk3576-qos", "syscon";
1244 compatible = "rockchip,rk3576-gmac", "snps,dwmac-4.20a";
1249 clock-names = "stmmaceth", "clk_mac_ref",
1254 interrupt-names = "macirq", "eth_wake_irq";
1255 power-domains = <&power RK3576_PD_SDGMAC>;
1257 reset-names = "stmmaceth";
1259 rockchip,php-grf = <&ioc_grf>;
1260 snps,axi-config = <&gmac0_stmmac_axi_setup>;
1261 snps,mixed-burst;
1262 snps,mtl-rx-config = <&gmac0_mtl_rx_setup>;
1263 snps,mtl-tx-config = <&gmac0_mtl_tx_setup>;
1268 compatible = "snps,dwmac-mdio";
1269 #address-cells = <0x1>;
1270 #size-cells = <0x0>;
1273 gmac0_stmmac_axi_setup: stmmac-axi-config {
1279 gmac0_mtl_rx_setup: rx-queues-config {
1280 snps,rx-queues-to-use = <1>;
1284 gmac0_mtl_tx_setup: tx-queues-config {
1285 snps,tx-queues-to-use = <1>;
1291 compatible = "rockchip,rk3576-gmac", "snps,dwmac-4.20a";
1296 clock-names = "stmmaceth", "clk_mac_ref",
1301 interrupt-names = "macirq", "eth_wake_irq";
1302 power-domains = <&power RK3576_PD_SDGMAC>;
1304 reset-names = "stmmaceth";
1306 rockchip,php-grf = <&ioc_grf>;
1307 snps,axi-config = <&gmac1_stmmac_axi_setup>;
1308 snps,mixed-burst;
1309 snps,mtl-rx-config = <&gmac1_mtl_rx_setup>;
1310 snps,mtl-tx-config = <&gmac1_mtl_tx_setup>;
1315 compatible = "snps,dwmac-mdio";
1316 #address-cells = <0x1>;
1317 #size-cells = <0x0>;
1320 gmac1_stmmac_axi_setup: stmmac-axi-config {
1326 gmac1_mtl_rx_setup: rx-queues-config {
1327 snps,rx-queues-to-use = <1>;
1331 gmac1_mtl_tx_setup: tx-queues-config {
1332 snps,tx-queues-to-use = <1>;
1338 compatible = "rockchip,rk3576-ufshc";
1344 reg-names = "hci", "mphy", "hci_grf", "mphy_grf", "hci_apb";
1347 clock-names = "core", "pclk", "pclk_mphy", "ref_out";
1348 assigned-clocks = <&cru CLK_REF_OSC_MPHY>;
1349 assigned-clock-parents = <&cru CLK_REF_MPHY_26M>;
1351 power-domains = <&power RK3576_PD_USB>;
1352 pinctrl-0 = <&ufs_refclk>;
1353 pinctrl-names = "default";
1356 reset-names = "biu", "sys", "ufs", "grf";
1357 reset-gpios = <&gpio4 RK_PD0 GPIO_ACTIVE_LOW>;
1366 clock-names = "clk_sfc", "hclk_sfc";
1367 #address-cells = <1>;
1368 #size-cells = <0>;
1373 compatible = "rockchip,rk3576-dw-mshc";
1376 clock-names = "biu", "ciu";
1377 fifo-depth = <0x100>;
1379 max-frequency = <200000000>;
1380 pinctrl-names = "default";
1381 pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_det &sdmmc0_bus4 &sdmmc0_pwren>;
1382 power-domains = <&power RK3576_PD_SDGMAC>;
1384 reset-names = "reset";
1389 compatible = "rockchip,rk3576-dwcmshc", "rockchip,rk3588-dwcmshc";
1391 assigned-clocks = <&cru BCLK_EMMC>, <&cru TCLK_EMMC>, <&cru CCLK_SRC_EMMC>;
1392 assigned-clock-rates = <200000000>, <24000000>, <200000000>;
1396 clock-names = "core", "bus", "axi", "block", "timer";
1398 max-frequency = <200000000>;
1399 pinctrl-0 = <&emmc_rstnout>, <&emmc_bus8>, <&emmc_clk>,
1401 pinctrl-names = "default";
1402 power-domains = <&power RK3576_PD_NVM>;
1406 reset-names = "core", "bus", "axi", "block", "timer";
1407 supports-cqe;
1416 clock-names = "clk_sfc", "hclk_sfc";
1417 #address-cells = <1>;
1418 #size-cells = <0>;
1423 compatible = "rockchip,rk3576-otp";
1425 #address-cells = <1>;
1426 #size-cells = <1>;
1429 clock-names = "otp", "apb_pclk", "phy";
1431 reset-names = "otp", "apb";
1434 cpu_code: cpu-code@2 {
1437 otp_cpu_version: cpu-version@5 {
1444 cpub_leakage: cpub-leakage@1e {
1447 cpul_leakage: cpul-leakage@1f {
1450 npu_leakage: npu-leakage@20 {
1453 gpu_leakage: gpu-leakage@21 {
1456 log_leakage: log-leakage@22 {
1461 gic: interrupt-controller@2a701000 {
1462 compatible = "arm,gic-400";
1468 interrupt-controller;
1469 #interrupt-cells = <3>;
1470 #address-cells = <2>;
1471 #size-cells = <2>;
1474 dmac0: dma-controller@2ab90000 {
1477 arm,pl330-periph-burst;
1479 clock-names = "apb_pclk";
1482 #dma-cells = <1>;
1485 dmac1: dma-controller@2abb0000 {
1488 arm,pl330-periph-burst;
1490 clock-names = "apb_pclk";
1493 #dma-cells = <1>;
1496 dmac2: dma-controller@2abd0000 {
1499 arm,pl330-periph-burst;
1501 clock-names = "apb_pclk";
1504 #dma-cells = <1>;
1508 compatible = "rockchip,rk3576-i2c", "rockchip,rk3399-i2c";
1511 clock-names = "i2c", "pclk";
1513 pinctrl-names = "default";
1514 pinctrl-0 = <&i2c1m0_xfer>;
1515 #address-cells = <1>;
1516 #size-cells = <0>;
1521 compatible = "rockchip,rk3576-i2c", "rockchip,rk3399-i2c";
1524 clock-names = "i2c", "pclk";
1526 pinctrl-names = "default";
1527 pinctrl-0 = <&i2c2m0_xfer>;
1528 #address-cells = <1>;
1529 #size-cells = <0>;
1534 compatible = "rockchip,rk3576-i2c", "rockchip,rk3399-i2c";
1537 clock-names = "i2c", "pclk";
1539 pinctrl-names = "default";
1540 pinctrl-0 = <&i2c3m0_xfer>;
1541 #address-cells = <1>;
1542 #size-cells = <0>;
1547 compatible = "rockchip,rk3576-i2c", "rockchip,rk3399-i2c";
1550 clock-names = "i2c", "pclk";
1552 pinctrl-names = "default";
1553 pinctrl-0 = <&i2c4m0_xfer>;
1554 #address-cells = <1>;
1555 #size-cells = <0>;
1560 compatible = "rockchip,rk3576-i2c", "rockchip,rk3399-i2c";
1563 clock-names = "i2c", "pclk";
1565 pinctrl-names = "default";
1566 pinctrl-0 = <&i2c5m0_xfer>;
1567 #address-cells = <1>;
1568 #size-cells = <0>;
1574 compatible = "rockchip,rk3576-i2c", "rockchip,rk3399-i2c";
1577 clock-names = "i2c", "pclk";
1579 pinctrl-names = "default";
1580 pinctrl-0 = <&i2c6m0_xfer>;
1581 #address-cells = <1>;
1582 #size-cells = <0>;
1587 compatible = "rockchip,rk3576-i2c", "rockchip,rk3399-i2c";
1590 clock-names = "i2c", "pclk";
1592 pinctrl-names = "default";
1593 pinctrl-0 = <&i2c7m0_xfer>;
1594 #address-cells = <1>;
1595 #size-cells = <0>;
1600 compatible = "rockchip,rk3576-i2c", "rockchip,rk3399-i2c";
1603 clock-names = "i2c", "pclk";
1605 pinctrl-names = "default";
1606 pinctrl-0 = <&i2c8m0_xfer>;
1607 #address-cells = <1>;
1608 #size-cells = <0>;
1613 compatible = "rockchip,rk3576-timer", "rockchip,rk3288-timer";
1616 clock-names = "pclk", "timer";
1621 compatible = "rockchip,rk3576-wdt", "snps,dw-wdt";
1624 clock-names = "tclk", "pclk";
1630 compatible = "rockchip,rk3576-spi", "rockchip,rk3066-spi";
1633 clock-names = "spiclk", "apb_pclk";
1635 dma-names = "tx", "rx";
1637 num-cs = <2>;
1638 pinctrl-names = "default";
1639 pinctrl-0 = <&spi0m0_csn0 &spi0m0_csn1 &spi0m0_pins>;
1640 #address-cells = <1>;
1641 #size-cells = <0>;
1646 compatible = "rockchip,rk3576-spi", "rockchip,rk3066-spi";
1649 clock-names = "spiclk", "apb_pclk";
1651 dma-names = "tx", "rx";
1653 num-cs = <2>;
1654 pinctrl-names = "default";
1655 pinctrl-0 = <&spi1m0_csn0 &spi1m0_csn1 &spi1m0_pins>;
1656 #address-cells = <1>;
1657 #size-cells = <0>;
1662 compatible = "rockchip,rk3576-spi", "rockchip,rk3066-spi";
1665 clock-names = "spiclk", "apb_pclk";
1667 dma-names = "tx", "rx";
1669 num-cs = <2>;
1670 pinctrl-names = "default";
1671 pinctrl-0 = <&spi2m0_csn0 &spi2m0_csn1 &spi2m0_pins>;
1672 #address-cells = <1>;
1673 #size-cells = <0>;
1678 compatible = "rockchip,rk3576-spi", "rockchip,rk3066-spi";
1681 clock-names = "spiclk", "apb_pclk";
1683 dma-names = "tx", "rx";
1685 num-cs = <2>;
1686 pinctrl-names = "default";
1687 pinctrl-0 = <&spi3m0_csn0 &spi3m0_csn1 &spi3m0_pins>;
1688 #address-cells = <1>;
1689 #size-cells = <0>;
1694 compatible = "rockchip,rk3576-spi", "rockchip,rk3066-spi";
1697 clock-names = "spiclk", "apb_pclk";
1699 dma-names = "tx", "rx";
1701 num-cs = <2>;
1702 pinctrl-names = "default";
1703 pinctrl-0 = <&spi4m0_csn0 &spi4m0_csn1 &spi4m0_pins>;
1704 #address-cells = <1>;
1705 #size-cells = <0>;
1710 compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart";
1712 reg-shift = <2>;
1713 reg-io-width = <4>;
1715 clock-names = "baudclk", "apb_pclk";
1717 dma-names = "tx", "rx";
1719 pinctrl-0 = <&uart0m0_xfer>;
1720 pinctrl-names = "default";
1725 compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart";
1727 reg-shift = <2>;
1728 reg-io-width = <4>;
1730 clock-names = "baudclk", "apb_pclk";
1732 dma-names = "tx", "rx";
1734 pinctrl-names = "default";
1735 pinctrl-0 = <&uart2m0_xfer>;
1740 compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart";
1742 reg-shift = <2>;
1743 reg-io-width = <4>;
1745 clock-names = "baudclk", "apb_pclk";
1747 dma-names = "tx", "rx";
1749 pinctrl-0 = <&uart3m0_xfer>;
1750 pinctrl-names = "default";
1755 compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart";
1757 reg-shift = <2>;
1758 reg-io-width = <4>;
1760 clock-names = "baudclk", "apb_pclk";
1762 dma-names = "tx", "rx";
1764 pinctrl-0 = <&uart4m0_xfer>;
1765 pinctrl-names = "default";
1770 compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart";
1772 reg-shift = <2>;
1773 reg-io-width = <4>;
1775 clock-names = "baudclk", "apb_pclk";
1777 dma-names = "tx", "rx";
1779 pinctrl-0 = <&uart5m0_xfer>;
1780 pinctrl-names = "default";
1785 compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart";
1787 reg-shift = <2>;
1788 reg-io-width = <4>;
1790 clock-names = "baudclk", "apb_pclk";
1792 dma-names = "tx", "rx";
1794 pinctrl-0 = <&uart6m0_xfer>;
1795 pinctrl-names = "default";
1800 compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart";
1802 reg-shift = <2>;
1803 reg-io-width = <4>;
1805 clock-names = "baudclk", "apb_pclk";
1807 dma-names = "tx", "rx";
1809 pinctrl-0 = <&uart7m0_xfer>;
1810 pinctrl-names = "default";
1815 compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart";
1817 reg-shift = <2>;
1818 reg-io-width = <4>;
1820 clock-names = "baudclk", "apb_pclk";
1822 dma-names = "tx", "rx";
1824 pinctrl-0 = <&uart8m0_xfer>;
1825 pinctrl-names = "default";
1830 compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart";
1832 reg-shift = <2>;
1833 reg-io-width = <4>;
1835 clock-names = "baudclk", "apb_pclk";
1837 dma-names = "tx", "rx";
1839 pinctrl-0 = <&uart9m0_xfer>;
1840 pinctrl-names = "default";
1845 compatible = "rockchip,rk3576-saradc", "rockchip,rk3588-saradc";
1848 clock-names = "saradc", "apb_pclk";
1851 reset-names = "saradc-apb";
1852 #io-channel-cells = <1>;
1857 compatible = "rockchip,rk3576-i2c", "rockchip,rk3399-i2c";
1860 clock-names = "i2c", "pclk";
1862 pinctrl-names = "default";
1863 pinctrl-0 = <&i2c9m0_xfer>;
1865 reset-names = "i2c", "apb";
1866 #address-cells = <1>;
1867 #size-cells = <0>;
1872 compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart";
1874 reg-shift = <2>;
1875 reg-io-width = <4>;
1877 clock-names = "baudclk", "apb_pclk";
1880 pinctrl-names = "default";
1881 pinctrl-0 = <&uart10m0_xfer>;
1886 compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart";
1888 reg-shift = <2>;
1889 reg-io-width = <4>;
1891 clock-names = "baudclk", "apb_pclk";
1894 pinctrl-names = "default";
1895 pinctrl-0 = <&uart11m0_xfer>;
1900 compatible = "rockchip,rk3576-naneng-combphy";
1902 #phy-cells = <1>;
1906 clock-names = "ref", "apb", "pipe";
1907 assigned-clocks = <&cru CLK_REF_PCIE0_PHY>;
1908 assigned-clock-rates = <100000000>;
1911 reset-names = "phy", "apb";
1912 rockchip,pipe-grf = <&php_grf>;
1913 rockchip,pipe-phy-grf = <&pipe_phy0_grf>;
1918 compatible = "rockchip,rk3576-naneng-combphy";
1920 #phy-cells = <1>;
1924 clock-names = "ref", "apb", "pipe";
1925 assigned-clocks = <&cru CLK_REF_PCIE1_PHY>;
1926 assigned-clock-rates = <100000000>;
1929 reset-names = "phy", "apb";
1930 rockchip,pipe-grf = <&php_grf>;
1931 rockchip,pipe-phy-grf = <&pipe_phy1_grf>;
1936 compatible = "rockchip,rk3576-usbdp-phy";
1938 #phy-cells = <1>;
1943 clock-names = "refclk", "immortal", "pclk", "utmi";
1949 reset-names = "init", "cmn", "lane", "pcs_apb", "pma_apb";
1950 rockchip,u2phy-grf = <&usb2phy_grf>;
1951 rockchip,usb-grf = <&usb_grf>;
1952 rockchip,usbdpphy-grf = <&usbdpphy_grf>;
1953 rockchip,vo-grf = <&vo1_grf>;
1958 compatible = "rockchip,rk3576-hdptx-phy", "rockchip,rk3588-hdptx-phy";
1961 clock-names = "ref", "apb";
1964 reset-names = "apb", "init", "cmn", "lane";
1966 #phy-cells = <0>;
1971 compatible = "mmio-sram";
1974 #address-cells = <1>;
1975 #size-cells = <1>;
1978 rkvdec_sram: rkvdec-sram@0 {
1983 scmi_shmem: scmi-shmem@4010f000 {
1984 compatible = "arm,scmi-shmem";
1989 compatible = "rockchip,rk3576-pinctrl";
1991 #address-cells = <2>;
1992 #size-cells = <2>;
1996 compatible = "rockchip,gpio-bank";
1999 gpio-controller;
2000 gpio-ranges = <&pinctrl 0 0 32>;
2002 interrupt-controller;
2003 #gpio-cells = <2>;
2004 #interrupt-cells = <2>;
2008 compatible = "rockchip,gpio-bank";
2011 gpio-controller;
2012 gpio-ranges = <&pinctrl 0 32 32>;
2014 interrupt-controller;
2015 #gpio-cells = <2>;
2016 #interrupt-cells = <2>;
2020 compatible = "rockchip,gpio-bank";
2023 gpio-controller;
2024 gpio-ranges = <&pinctrl 0 64 32>;
2026 interrupt-controller;
2027 #gpio-cells = <2>;
2028 #interrupt-cells = <2>;
2032 compatible = "rockchip,gpio-bank";
2035 gpio-controller;
2036 gpio-ranges = <&pinctrl 0 96 32>;
2038 interrupt-controller;
2039 #gpio-cells = <2>;
2040 #interrupt-cells = <2>;
2044 compatible = "rockchip,gpio-bank";
2047 gpio-controller;
2048 gpio-ranges = <&pinctrl 0 128 32>;
2050 interrupt-controller;
2051 #gpio-cells = <2>;
2052 #interrupt-cells = <2>;
2058 #include "rk3576-pinctrl.dtsi"