dts/rockchip/rk3528.dtsi

1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/clock/rockchip,rk3528-cru.h>
12 #include <dt-bindings/reset/rockchip,rk3528-cru.h>
17 	interrupt-parent = <&gic>;
18 	#address-cells = <2>;
19 	#size-cells = <2>;
38 		#address-cells = <1>;
39 		#size-cells = <0>;
41 		cpu-map {
59 			compatible = "arm,cortex-a53";
60 			reg = <0x0>;
62 			enable-method = "psci";
67 			compatible = "arm,cortex-a53";
68 			reg = <0x1>;
70 			enable-method = "psci";
75 			compatible = "arm,cortex-a53";
76 			reg = <0x2>;
78 			enable-method = "psci";
83 			compatible = "arm,cortex-a53";
84 			reg = <0x3>;
86 			enable-method = "psci";
93 			compatible = "arm,scmi-smc";
94 			arm,smc-id = <0x82000010>;
96 			#address-cells = <1>;
97 			#size-cells = <0>;
100 				reg = <0x14>;
101 				#clock-cells = <1>;
107 		compatible = "arm,psci-1.0", "arm,psci-0.2";
111 	reserved-memory {
112 		#address-cells = <2>;
113 		#size-cells = <2>;
117 			compatible = "arm,scmi-shmem";
118 			reg = <0x0 0x0010f000 0x0 0x100>;
119 			no-map;
124 		compatible = "arm,armv8-timer";
131 	xin24m: clock-xin24m {
132 		compatible = "fixed-clock";
133 		clock-frequency = <24000000>;
134 		clock-output-names = "xin24m";
135 		#clock-cells = <0>;
138 	gmac0_clk: clock-gmac50m {
139 		compatible = "fixed-clock";
140 		clock-frequency = <50000000>;
141 		clock-output-names = "gmac0";
142 		#clock-cells = <0>;
146 		compatible = "simple-bus";
148 		#address-cells = <2>;
149 		#size-cells = <2>;
151 		gic: interrupt-controller@fed01000 {
152 			compatible = "arm,gic-400";
153 			reg = <0x0 0xfed01000 0 0x1000>,
159 			interrupt-controller;
160 			#address-cells = <0>;
161 			#interrupt-cells = <3>;
165 			compatible = "rockchip,rk3528-qos", "syscon";
166 			reg = <0x0 0xff200000 0x0 0x20>;
170 			compatible = "rockchip,rk3528-qos", "syscon";
171 			reg = <0x0 0xff200080 0x0 0x20>;
175 			compatible = "rockchip,rk3528-qos", "syscon";
176 			reg = <0x0 0xff200100 0x0 0x20>;
180 			compatible = "rockchip,rk3528-qos", "syscon";
181 			reg = <0x0 0xff200200 0x0 0x20>;
185 			compatible = "rockchip,rk3528-qos", "syscon";
186 			reg = <0x0 0xff200280 0x0 0x20>;
190 			compatible = "rockchip,rk3528-qos", "syscon";
191 			reg = <0x0 0xff200300 0x0 0x20>;
195 			compatible = "rockchip,rk3528-qos", "syscon";
196 			reg = <0x0 0xff200380 0x0 0x20>;
200 			compatible = "rockchip,rk3528-qos", "syscon";
201 			reg = <0x0 0xff210000 0x0 0x20>;
205 			compatible = "rockchip,rk3528-qos", "syscon";
206 			reg = <0x0 0xff210080 0x0 0x20>;
210 			compatible = "rockchip,rk3528-qos", "syscon";
211 			reg = <0x0 0xff220000 0x0 0x20>;
215 			compatible = "rockchip,rk3528-qos", "syscon";
216 			reg = <0x0 0xff220080 0x0 0x20>;
220 			compatible = "rockchip,rk3528-qos", "syscon";
221 			reg = <0x0 0xff240000 0x0 0x20>;
225 			compatible = "rockchip,rk3528-qos", "syscon";
226 			reg = <0x0 0xff250000 0x0 0x20>;
230 			compatible = "rockchip,rk3528-qos", "syscon";
231 			reg = <0x0 0xff260000 0x0 0x20>;
235 			compatible = "rockchip,rk3528-qos", "syscon";
236 			reg = <0x0 0xff270000 0x0 0x20>;
240 			compatible = "rockchip,rk3528-qos", "syscon";
241 			reg = <0x0 0xff270080 0x0 0x20>;
245 			compatible = "rockchip,rk3528-qos", "syscon";
246 			reg = <0x0 0xff270100 0x0 0x20>;
250 			compatible = "rockchip,rk3528-qos", "syscon";
251 			reg = <0x0 0xff270200 0x0 0x20>;
255 			compatible = "rockchip,rk3528-qos", "syscon";
256 			reg = <0x0 0xff270280 0x0 0x20>;
260 			compatible = "rockchip,rk3528-qos", "syscon";
261 			reg = <0x0 0xff270300 0x0 0x20>;
265 			compatible = "rockchip,rk3528-qos", "syscon";
266 			reg = <0x0 0xff270380 0x0 0x20>;
270 			compatible = "rockchip,rk3528-qos", "syscon";
271 			reg = <0x0 0xff270480 0x0 0x20>;
275 			compatible = "rockchip,rk3528-qos", "syscon";
276 			reg = <0x0 0xff270500 0x0 0x20>;
280 			compatible = "rockchip,rk3528-qos", "syscon";
281 			reg = <0x0 0xff280000 0x0 0x20>;
285 			compatible = "rockchip,rk3528-qos", "syscon";
286 			reg = <0x0 0xff280080 0x0 0x20>;
290 			compatible = "rockchip,rk3528-qos", "syscon";
291 			reg = <0x0 0xff280100 0x0 0x20>;
295 			compatible = "rockchip,rk3528-qos", "syscon";
296 			reg = <0x0 0xff280180 0x0 0x20>;
300 			compatible = "rockchip,rk3528-qos", "syscon";
301 			reg = <0x0 0xff280200 0x0 0x20>;
305 			compatible = "rockchip,rk3528-qos", "syscon";
306 			reg = <0x0 0xff280280 0x0 0x20>;
310 			compatible = "rockchip,rk3528-qos", "syscon";
311 			reg = <0x0 0xff280300 0x0 0x20>;
315 			compatible = "rockchip,rk3528-qos", "syscon";
316 			reg = <0x0 0xff280380 0x0 0x20>;
320 			compatible = "rockchip,rk3528-qos", "syscon";
321 			reg = <0x0 0xff280400 0x0 0x20>;
324 		cru: clock-controller@ff4a0000 {
325 			compatible = "rockchip,rk3528-cru";
326 			reg = <0x0 0xff4a0000 0x0 0x30000>;
327 			assigned-clocks =
344 			assigned-clock-rates =
362 			clock-names = "xin24m", "gmac0";
363 			#clock-cells = <1>;
364 			#reset-cells = <1>;
368 			compatible = "rockchip,rk3528-ioc-grf", "syscon";
369 			reg = <0x0 0xff540000 0x0 0x40000>;
373 			compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart";
374 			reg = <0x0 0xff9f0000 0x0 0x100>;
376 			clock-names = "baudclk", "apb_pclk";
378 			reg-io-width = <4>;
379 			reg-shift = <2>;
384 			compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart";
385 			reg = <0x0 0xff9f8000 0x0 0x100>;
387 			clock-names = "baudclk", "apb_pclk";
389 			reg-io-width = <4>;
390 			reg-shift = <2>;
395 			compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart";
396 			reg = <0x0 0xffa00000 0x0 0x100>;
398 			clock-names = "baudclk", "apb_pclk";
400 			reg-io-width = <4>;
401 			reg-shift = <2>;
406 			compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart";
408 			clock-names = "baudclk", "apb_pclk";
409 			reg = <0x0 0xffa08000 0x0 0x100>;
410 			reg-io-width = <4>;
411 			reg-shift = <2>;
416 			compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart";
417 			reg = <0x0 0xffa10000 0x0 0x100>;
419 			clock-names = "baudclk", "apb_pclk";
421 			reg-io-width = <4>;
422 			reg-shift = <2>;
427 			compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart";
428 			reg = <0x0 0xffa18000 0x0 0x100>;
430 			clock-names = "baudclk", "apb_pclk";
432 			reg-io-width = <4>;
433 			reg-shift = <2>;
438 			compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart";
439 			reg = <0x0 0xffa20000 0x0 0x100>;
441 			clock-names = "baudclk", "apb_pclk";
443 			reg-io-width = <4>;
444 			reg-shift = <2>;
449 			compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart";
450 			reg = <0x0 0xffa28000 0x0 0x100>;
452 			clock-names = "baudclk", "apb_pclk";
454 			reg-io-width = <4>;
455 			reg-shift = <2>;
460 			compatible = "rockchip,rk3528-saradc";
461 			reg = <0x0 0xffae0000 0x0 0x10000>;
463 			clock-names = "saradc", "apb_pclk";
466 			reset-names = "saradc-apb";
467 			#io-channel-cells = <1>;
472 			compatible = "rockchip,rk3528-dwcmshc",
473 				     "rockchip,rk3588-dwcmshc";
474 			reg = <0x0 0xffbf0000 0x0 0x10000>;
475 			assigned-clocks = <&cru BCLK_EMMC>, <&cru TCLK_EMMC>,
477 			assigned-clock-rates = <200000000>, <24000000>,
482 			clock-names = "core", "bus", "axi", "block", "timer";
484 			max-frequency = <200000000>;
485 			pinctrl-names = "default";
486 			pinctrl-0 = <&emmc_bus8>, <&emmc_clk>, <&emmc_cmd>,
491 			reset-names = "core", "bus", "axi", "block", "timer";
496 			compatible = "rockchip,rk3528-pinctrl";
498 			#address-cells = <2>;
499 			#size-cells = <2>;
503 				compatible = "rockchip,gpio-bank";
504 				reg = <0x0 0xff610000 0x0 0x200>;
507 				gpio-controller;
508 				#gpio-cells = <2>;
509 				gpio-ranges = <&pinctrl 0 0 32>;
510 				interrupt-controller;
511 				#interrupt-cells = <2>;
515 				compatible = "rockchip,gpio-bank";
516 				reg = <0x0 0xffaf0000 0x0 0x200>;
519 				gpio-controller;
520 				#gpio-cells = <2>;
521 				gpio-ranges = <&pinctrl 0 32 32>;
522 				interrupt-controller;
523 				#interrupt-cells = <2>;
527 				compatible = "rockchip,gpio-bank";
528 				reg = <0x0 0xffb00000 0x0 0x200>;
531 				gpio-controller;
532 				#gpio-cells = <2>;
533 				gpio-ranges = <&pinctrl 0 64 32>;
534 				interrupt-controller;
535 				#interrupt-cells = <2>;
539 				compatible = "rockchip,gpio-bank";
540 				reg = <0x0 0xffb10000 0x0 0x200>;
543 				gpio-controller;
544 				#gpio-cells = <2>;
545 				gpio-ranges = <&pinctrl 0 96 32>;
546 				interrupt-controller;
547 				#interrupt-cells = <2>;
551 				compatible = "rockchip,gpio-bank";
552 				reg = <0x0 0xffb20000 0x0 0x200>;
555 				gpio-controller;
556 				#gpio-cells = <2>;
557 				gpio-ranges = <&pinctrl 0 128 32>;
558 				interrupt-controller;
559 				#interrupt-cells = <2>;
565 #include "rk3528-pinctrl.dtsi"