Lines Matching +full:gpt +full:- +full:u0 +full:- +full:gtciada
1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
8 #include <dt-bindings/clock/renesas,r9a09g057-cpg.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #address-cells = <2>;
14 #size-cells = <2>;
16 audio_extal_clk: audio-clk {
17 compatible = "fixed-clock";
18 #clock-cells = <0>;
20 clock-frequency = <0>;
30 cluster0_opp: opp-table-0 {
31 compatible = "operating-points-v2";
33 opp-1700000000 {
34 opp-hz = /bits/ 64 <1700000000>;
35 opp-microvolt = <900000>;
36 clock-latency-ns = <300000>;
38 opp-850000000 {
39 opp-hz = /bits/ 64 <850000000>;
40 opp-microvolt = <800000>;
41 clock-latency-ns = <300000>;
43 opp-425000000 {
44 opp-hz = /bits/ 64 <425000000>;
45 opp-microvolt = <800000>;
46 clock-latency-ns = <300000>;
48 opp-212500000 {
49 opp-hz = /bits/ 64 <212500000>;
50 opp-microvolt = <800000>;
51 clock-latency-ns = <300000>;
52 opp-suspend;
57 #address-cells = <1>;
58 #size-cells = <0>;
61 compatible = "arm,cortex-a55";
64 next-level-cache = <&L3_CA55>;
65 enable-method = "psci";
67 operating-points-v2 = <&cluster0_opp>;
71 compatible = "arm,cortex-a55";
74 next-level-cache = <&L3_CA55>;
75 enable-method = "psci";
77 operating-points-v2 = <&cluster0_opp>;
81 compatible = "arm,cortex-a55";
84 next-level-cache = <&L3_CA55>;
85 enable-method = "psci";
87 operating-points-v2 = <&cluster0_opp>;
91 compatible = "arm,cortex-a55";
94 next-level-cache = <&L3_CA55>;
95 enable-method = "psci";
97 operating-points-v2 = <&cluster0_opp>;
100 L3_CA55: cache-controller-0 {
102 cache-unified;
103 cache-size = <0x100000>;
104 cache-level = <3>;
108 gpu_opp_table: opp-table-1 {
109 compatible = "operating-points-v2";
111 opp-630000000 {
112 opp-hz = /bits/ 64 <630000000>;
113 opp-microvolt = <800000>;
116 opp-315000000 {
117 opp-hz = /bits/ 64 <315000000>;
118 opp-microvolt = <800000>;
121 opp-157500000 {
122 opp-hz = /bits/ 64 <157500000>;
123 opp-microvolt = <800000>;
126 opp-78750000 {
127 opp-hz = /bits/ 64 <78750000>;
128 opp-microvolt = <800000>;
131 opp-19687500 {
132 opp-hz = /bits/ 64 <19687500>;
133 opp-microvolt = <800000>;
138 compatible = "arm,psci-1.0", "arm,psci-0.2";
142 qextal_clk: qextal-clk {
143 compatible = "fixed-clock";
144 #clock-cells = <0>;
146 clock-frequency = <0>;
149 rtxin_clk: rtxin-clk {
150 compatible = "fixed-clock";
151 #clock-cells = <0>;
153 clock-frequency = <0>;
157 compatible = "simple-bus";
158 interrupt-parent = <&gic>;
159 #address-cells = <2>;
160 #size-cells = <2>;
163 icu: interrupt-controller@10400000 {
164 compatible = "renesas,r9a09g057-icu";
166 #interrupt-cells = <2>;
167 #address-cells = <0>;
168 interrupt-controller;
227 interrupt-names = "nmi",
242 "int-ca55-0", "int-ca55-1",
243 "int-ca55-2", "int-ca55-3",
244 "icu-error-ca55",
245 "gpt-u0-gtciada", "gpt-u0-gtciadb",
246 "gpt-u1-gtciada", "gpt-u1-gtciadb";
248 power-domains = <&cpg>;
253 compatible = "renesas,r9a09g057-pinctrl";
256 gpio-controller;
257 #gpio-cells = <2>;
258 gpio-ranges = <&pinctrl 0 0 96>;
259 #interrupt-cells = <2>;
260 interrupt-controller;
261 interrupt-parent = <&icu>;
262 power-domains = <&cpg>;
266 cpg: clock-controller@10420000 {
267 compatible = "renesas,r9a09g057-cpg";
270 clock-names = "audio_extal", "rtxin", "qextal";
271 #clock-cells = <2>;
272 #reset-cells = <1>;
273 #power-domain-cells = <0>;
276 sys: system-controller@10430000 {
277 compatible = "renesas,r9a09g057-sys";
284 compatible = "renesas,r9a09g057-ostm", "renesas,ostm";
289 power-domains = <&cpg>;
294 compatible = "renesas,r9a09g057-ostm", "renesas,ostm";
299 power-domains = <&cpg>;
304 compatible = "renesas,r9a09g057-ostm", "renesas,ostm";
309 power-domains = <&cpg>;
314 compatible = "renesas,r9a09g057-ostm", "renesas,ostm";
319 power-domains = <&cpg>;
324 compatible = "renesas,r9a09g057-ostm", "renesas,ostm";
329 power-domains = <&cpg>;
334 compatible = "renesas,r9a09g057-ostm", "renesas,ostm";
339 power-domains = <&cpg>;
344 compatible = "renesas,r9a09g057-ostm", "renesas,ostm";
349 power-domains = <&cpg>;
354 compatible = "renesas,r9a09g057-ostm", "renesas,ostm";
359 power-domains = <&cpg>;
364 compatible = "renesas,r9a09g057-wdt";
367 clock-names = "pclk", "oscclk";
369 power-domains = <&cpg>;
374 compatible = "renesas,r9a09g057-wdt";
377 clock-names = "pclk", "oscclk";
379 power-domains = <&cpg>;
384 compatible = "renesas,r9a09g057-wdt";
387 clock-names = "pclk", "oscclk";
389 power-domains = <&cpg>;
394 compatible = "renesas,r9a09g057-wdt";
397 clock-names = "pclk", "oscclk";
399 power-domains = <&cpg>;
404 compatible = "renesas,scif-r9a09g057";
415 interrupt-names = "eri", "rxi", "txi", "bri", "dri",
416 "tei", "tei-dri", "rxi-edge", "txi-edge";
418 clock-names = "fck";
419 power-domains = <&cpg>;
425 compatible = "renesas,riic-r9a09g057";
435 interrupt-names = "tei", "ri", "ti", "spi", "sti",
439 power-domains = <&cpg>;
440 #address-cells = <1>;
441 #size-cells = <0>;
446 compatible = "renesas,riic-r9a09g057";
456 interrupt-names = "tei", "ri", "ti", "spi", "sti",
460 power-domains = <&cpg>;
461 #address-cells = <1>;
462 #size-cells = <0>;
467 compatible = "renesas,riic-r9a09g057";
477 interrupt-names = "tei", "ri", "ti", "spi", "sti",
481 power-domains = <&cpg>;
482 #address-cells = <1>;
483 #size-cells = <0>;
488 compatible = "renesas,riic-r9a09g057";
498 interrupt-names = "tei", "ri", "ti", "spi", "sti",
502 power-domains = <&cpg>;
503 #address-cells = <1>;
504 #size-cells = <0>;
509 compatible = "renesas,riic-r9a09g057";
519 interrupt-names = "tei", "ri", "ti", "spi", "sti",
523 power-domains = <&cpg>;
524 #address-cells = <1>;
525 #size-cells = <0>;
530 compatible = "renesas,riic-r9a09g057";
540 interrupt-names = "tei", "ri", "ti", "spi", "sti",
544 power-domains = <&cpg>;
545 #address-cells = <1>;
546 #size-cells = <0>;
551 compatible = "renesas,riic-r9a09g057";
561 interrupt-names = "tei", "ri", "ti", "spi", "sti",
565 power-domains = <&cpg>;
566 #address-cells = <1>;
567 #size-cells = <0>;
572 compatible = "renesas,riic-r9a09g057";
582 interrupt-names = "tei", "ri", "ti", "spi", "sti",
586 power-domains = <&cpg>;
587 #address-cells = <1>;
588 #size-cells = <0>;
593 compatible = "renesas,riic-r9a09g057";
603 interrupt-names = "tei", "ri", "ti", "spi", "sti",
607 power-domains = <&cpg>;
608 #address-cells = <1>;
609 #size-cells = <0>;
614 compatible = "renesas,r9a09g057-mali",
615 "arm,mali-bifrost";
621 interrupt-names = "job", "mmu", "gpu", "event";
625 clock-names = "gpu", "bus", "bus_ace";
626 power-domains = <&cpg>;
630 reset-names = "rst", "axi_rst", "ace_rst";
631 operating-points-v2 = <&gpu_opp_table>;
635 gic: interrupt-controller@14900000 {
636 compatible = "arm,gic-v3";
639 #interrupt-cells = <3>;
640 #address-cells = <0>;
641 interrupt-controller;
646 compatible = "renesas,sdhi-r9a09g057";
652 clock-names = "core", "clkh", "cd", "aclk";
654 power-domains = <&cpg>;
659 compatible = "renesas,sdhi-r9a09g057";
665 clock-names = "core", "clkh", "cd", "aclk";
667 power-domains = <&cpg>;
672 compatible = "renesas,sdhi-r9a09g057";
678 clock-names = "core", "clkh", "cd", "aclk";
680 power-domains = <&cpg>;
686 compatible = "arm,armv8-timer";
687 interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
692 interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", "hyp-virt";