dts/marvell/armada-ap806-quad.dtsi

1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 #include "armada-ap806.dtsi"
12 		#address-cells = <1>;
13 		#size-cells = <0>;
17 			compatible = "arm,cortex-a72";
19 			enable-method = "psci";
20 			#cooling-cells = <2>;
22 			i-cache-size = <0xc000>;
23 			i-cache-line-size = <64>;
24 			i-cache-sets = <256>;
25 			d-cache-size = <0x8000>;
26 			d-cache-line-size = <64>;
27 			d-cache-sets = <256>;
28 			next-level-cache = <&l2_0>;
32 			compatible = "arm,cortex-a72";
34 			enable-method = "psci";
35 			#cooling-cells = <2>;
37 			i-cache-size = <0xc000>;
38 			i-cache-line-size = <64>;
39 			i-cache-sets = <256>;
40 			d-cache-size = <0x8000>;
41 			d-cache-line-size = <64>;
42 			d-cache-sets = <256>;
43 			next-level-cache = <&l2_0>;
47 			compatible = "arm,cortex-a72";
49 			enable-method = "psci";
50 			#cooling-cells = <2>;
52 			i-cache-size = <0xc000>;
53 			i-cache-line-size = <64>;
54 			i-cache-sets = <256>;
55 			d-cache-size = <0x8000>;
56 			d-cache-line-size = <64>;
57 			d-cache-sets = <256>;
58 			next-level-cache = <&l2_1>;
62 			compatible = "arm,cortex-a72";
64 			enable-method = "psci";
65 			#cooling-cells = <2>;
67 			i-cache-size = <0xc000>;
68 			i-cache-line-size = <64>;
69 			i-cache-sets = <256>;
70 			d-cache-size = <0x8000>;
71 			d-cache-line-size = <64>;
72 			d-cache-sets = <256>;
73 			next-level-cache = <&l2_1>;
76 		l2_0: l2-cache0 {
77 			compatible = "cache";
78 			cache-size = <0x80000>;
79 			cache-line-size = <64>;
80 			cache-sets = <512>;
81 			cache-level = <2>;
82 			cache-unified;
85 		l2_1: l2-cache1 {
86 			compatible = "cache";
87 			cache-size = <0x80000>;
88 			cache-line-size = <64>;
89 			cache-sets = <512>;
90 			cache-level = <2>;
91 			cache-unified;