Lines Matching +full:assigned +full:- +full:clock +full:- +full:rates

1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 	assigned-clocks = <&clk IMX8MP_CLK_A53_SRC>,
13 	assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
19 	assigned-clock-rates = <0>, <0>,
24 	fsl,operating-mode = "nominal";
28 	assigned-clocks = <&clk IMX8MP_CLK_GPU2D_CORE>;
29 	assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>;
30 	assigned-clock-rates = <800000000>;
34 	assigned-clocks = <&clk IMX8MP_CLK_GPU3D_CORE>,
36 	assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
38 	assigned-clock-rates = <800000000>, <800000000>;
42 	assigned-clocks = <&clk IMX8MP_CLK_HDMI_AXI>,
44 	assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
46 	assigned-clock-rates = <400000000>, <133000000>;
50 	assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>;
51 	assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>;
52 	assigned-clock-rates = <400000000>;
56 	assigned-clocks = <&clk IMX8MP_CLK_GPU_AXI>,
58 	assigned-clock-parents = <&clk IMX8MP_SYS_PLL3_OUT>,
60 	assigned-clock-rates = <600000000>, <300000000>;
64 	assigned-clocks = <&clk IMX8MP_CLK_ML_CORE>,
67 	assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
70 	assigned-clock-rates = <800000000>,
76 	assigned-clocks = <&clk IMX8MP_CLK_MEDIA_AXI>,
82 	assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
87 	assigned-clock-rates = <400000000>, <200000000>,
92 /delete-node/ &{noc_opp_table/opp-1000000000};