dts/freescale/imx8-ss-hsio.dtsi

1 // SPDX-License-Identifier: GPL-2.0+
7 #include <dt-bindings/phy/phy.h>
9 hsio_axi_clk: clock-hsio-axi {
10 	compatible = "fixed-clock";
11 	#clock-cells = <0>;
12 	clock-frequency = <400000000>;
13 	clock-output-names = "hsio_axi_clk";
16 hsio_per_clk: clock-hsio-per {
17 	compatible = "fixed-clock";
18 	#clock-cells = <0>;
19 	clock-frequency = <133333333>;
20 	clock-output-names = "hsio_per_clk";
23 hsio_refa_clk: clock-hsio-refa {
24 	compatible = "gpio-gate-clock";
26 	#clock-cells = <0>;
27 	enable-gpios = <&lsio_gpio4 27 GPIO_ACTIVE_LOW>;
30 hsio_refb_clk: clock-hsio-refb {
31 	compatible = "gpio-gate-clock";
33 	#clock-cells = <0>;
34 	enable-gpios = <&lsio_gpio4 1 GPIO_ACTIVE_LOW>;
37 xtal100m: clock-xtal100m {
38 	compatible = "fixed-clock";
39 	#clock-cells = <0>;
40 	clock-frequency = <100000000>;
41 	clock-output-names = "xtal_100MHz";
45 	compatible = "simple-bus";
48 	#address-cells = <1>;
49 	#size-cells = <1>;
50 	dma-ranges = <0x80000000 0 0x80000000 0x80000000>;
53 		compatible = "fsl,imx8q-pcie";
56 		reg-names = "dbi", "config";
59 		#interrupt-cells = <1>;
62 		interrupt-names = "msi", "dma";
63 		#address-cells = <3>;
64 		#size-cells = <2>;
68 		clock-names = "dbi", "mstr", "slv";
69 		bus-range = <0x00 0xff>;
71 		interrupt-map = <0 0 0 1 &gic 0 105 4>,
75 		interrupt-map-mask = <0 0 0 0x7>;
76 		num-lanes = <1>;
77 		num-viewport = <4>;
78 		power-domains = <&pd IMX_SC_R_PCIE_B>;
79 		fsl,max-link-speed = <3>;
83 	pcieb_ep: pcie-ep@5f010000 {
84 		compatible = "fsl,imx8q-pcie-ep";
87 		reg-names = "dbi", "addr_space";
88 		num-lanes = <1>;
90 		interrupt-names = "dma";
94 		clock-names = "dbi", "mstr", "slv";
95 		power-domains = <&pd IMX_SC_R_PCIE_B>;
96 		fsl,max-link-speed = <3>;
97 		num-ib-windows = <6>;
98 		num-ob-windows = <6>;
102 	pcieb_lpcg: clock-controller@5f060000 {
103 		compatible = "fsl,imx8qxp-lpcg";
106 		#clock-cells = <1>;
107 		clock-indices = <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>, <IMX_LPCG_CLK_6>;
108 		clock-output-names = "hsio_pcieb_mstr_axi_clk",
111 		power-domains = <&pd IMX_SC_R_PCIE_B>;
114 	phyx1_crr1_lpcg: clock-controller@5f0b0000 {
115 		compatible = "fsl,imx8qxp-lpcg";
118 		#clock-cells = <1>;
119 		clock-indices = <IMX_LPCG_CLK_4>;
120 		clock-output-names = "hsio_phyx1_per_clk";
121 		power-domains = <&pd IMX_SC_R_SERDES_1>;
124 	pcieb_crr3_lpcg: clock-controller@5f0d0000 {
125 		compatible = "fsl,imx8qxp-lpcg";
128 		#clock-cells = <1>;
129 		clock-indices = <IMX_LPCG_CLK_4>;
130 		clock-output-names = "hsio_pcieb_per_clk";
131 		power-domains = <&pd IMX_SC_R_PCIE_B>;
134 	misc_crr5_lpcg: clock-controller@5f0f0000 {
135 		compatible = "fsl,imx8qxp-lpcg";
138 		#clock-cells = <1>;
139 		clock-indices = <IMX_LPCG_CLK_4>;
140 		clock-output-names = "hsio_misc_per_clk";
141 		power-domains = <&pd IMX_SC_R_HSIO_GPIO>;