dts/apple/t8012.dtsi

1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/interrupt-controller/apple-aic.h>
12 #include <dt-bindings/interrupt-controller/irq.h>
13 #include <dt-bindings/pinctrl/apple.h>
16 	interrupt-parent = <&aic>;
17 	#address-cells = <2>;
18 	#size-cells = <2>;
20 	clkref: clock-ref {
21 		compatible = "fixed-clock";
22 		#clock-cells = <0>;
23 		clock-frequency = <24000000>;
24 		clock-output-names = "clkref";
28 		#address-cells = <2>;
29 		#size-cells = <0>;
31 		cpu0: cpu@10000 {
32 			compatible = "apple,hurricane-zephyr";
34 			cpu-release-addr = <0 0>; /* To be filled by loader */
35 			operating-points-v2 = <&fusion_opp>;
36 			performance-domains = <&cpufreq>;
37 			enable-method = "spin-table";
38 			device_type = "cpu";
41 		cpu1: cpu@10001 {
42 			compatible = "apple,hurricane-zephyr";
44 			cpu-release-addr = <0 0>; /* To be filled by loader */
45 			operating-points-v2 = <&fusion_opp>;
46 			performance-domains = <&cpufreq>;
47 			enable-method = "spin-table";
48 			device_type = "cpu";
52 	fusion_opp: opp-table {
53 		compatible = "operating-points-v2";
57 		 * that use p-state transitions to switch between cores.
60 		 * The E-core frequencies are adjusted so performance scales
65 			opp-hz = /bits/ 64 <172000000>; /* 300 MHz, E-core */
66 			opp-level = <1>;
67 			clock-latency-ns = <11000>;
70 			opp-hz = /bits/ 64 <230000000>; /* 396 MHz, E-core */
71 			opp-level = <2>;
72 			clock-latency-ns = <140000>;
75 			opp-hz = /bits/ 64 <425000000>; /* 732 MHz, E-core */
76 			opp-level = <3>;
77 			clock-latency-ns = <110000>;
80 			opp-hz = /bits/ 64 <637000000>; /* 1092 MHz, E-core */
81 			opp-level = <4>;
82 			clock-latency-ns = <130000>;
85 			opp-hz = /bits/ 64 <756000000>;
86 			opp-level = <5>;
87 			clock-latency-ns = <130000>;
90 			opp-hz = /bits/ 64 <1056000000>;
91 			opp-level = <6>;
92 			clock-latency-ns = <130000>;
95 			opp-hz = /bits/ 64 <1356000000>;
96 			opp-level = <7>;
97 			clock-latency-ns = <130000>;
100 			opp-hz = /bits/ 64 <1644000000>;
101 			opp-level = <8>;
102 			clock-latency-ns = <135000>;
105 			opp-hz = /bits/ 64 <1944000000>;
106 			opp-level = <9>;
107 			clock-latency-ns = <140000>;
110 			opp-hz = /bits/ 64 <2244000000>;
111 			opp-level = <10>;
112 			clock-latency-ns = <150000>;
115 		/* Not available until CPU deep sleep is implemented */
117 			opp-hz = /bits/ 64 <2340000000>;
118 			opp-level = <11>;
119 			clock-latency-ns = <150000>;
120 			turbo-mode;
126 		compatible = "simple-bus";
127 		#address-cells = <2>;
128 		#size-cells = <2>;
129 		nonposted-mmio;
132 		cpufreq: performance-controller@202f20000 {
133 …compatible = "apple,t8010-cluster-cpufreq", "apple,t8103-cluster-cpufreq", "apple,cluster-cpufreq";
135 			#performance-domain-cells = <0>;
139 			compatible = "apple,s5l-uart";
141 			reg-io-width = <4>;
142 			interrupt-parent = <&aic>;
144 			/* Use the bootloader-enabled clocks for now. */
146 			clock-names = "uart", "clk_uart_baud0";
147 			power-domains = <&ps_uart0>;
151 		pmgr: power-management@20e000000 {
152 			compatible = "apple,t8010-pmgr", "apple,pmgr", "syscon", "simple-mfd";
153 			#address-cells = <1>;
154 			#size-cells = <1>;
159 		aic: interrupt-controller@20e100000 {
160 			compatible = "apple,t8010-aic", "apple,aic";
162 			#interrupt-cells = <3>;
163 			interrupt-controller;
164 			power-domains = <&ps_aic>;
168 			compatible = "apple,t8010-pinctrl", "apple,pinctrl";
170 			power-domains = <&ps_gpio>;
172 			gpio-controller;
173 			#gpio-cells = <2>;
174 			gpio-ranges = <&pinctrl_ap 0 0 221>;
177 			interrupt-controller;
178 			#interrupt-cells = <2>;
179 			interrupt-parent = <&aic>;
190 			compatible = "apple,t8010-pinctrl", "apple,pinctrl";
193 			gpio-controller;
194 			#gpio-cells = <2>;
195 			gpio-ranges = <&pinctrl_aop 0 0 41>;
198 			interrupt-controller;
199 			#interrupt-cells = <2>;
200 			interrupt-parent = <&aic>;
211 			compatible = "apple,t8010-pinctrl", "apple,pinctrl";
214 			gpio-controller;
215 			#gpio-cells = <2>;
216 			gpio-ranges = <&pinctrl_nub 0 0 19>;
219 			interrupt-controller;
220 			#interrupt-cells = <2>;
221 			interrupt-parent = <&aic>;
227 		pmgr_mini: power-management@211200000 {
228 			compatible = "apple,t8010-pmgr", "apple,pmgr", "syscon", "simple-mfd";
229 			#address-cells = <1>;
230 			#size-cells = <1>;
236 			compatible = "apple,t8010-wdt", "apple,wdt";
239 			interrupt-parent = <&aic>;
244 			compatible = "apple,t8010-pinctrl", "apple,pinctrl";
246 			power-domains = <&ps_smc_cpu>;
248 			gpio-controller;
249 			#gpio-cells = <2>;
250 			gpio-ranges = <&pinctrl_smc 0 0 81>;
253 			interrupt-controller;
254 			#interrupt-cells = <2>;
255 			interrupt-parent = <&aic>;
272 		compatible = "arm,armv8-timer";
273 		interrupt-parent = <&aic>;
274 		interrupt-names = "phys", "virt";
281 #include "t8012-pmgr.dtsi"