dts/apple/s8001.dtsi

1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/interrupt-controller/apple-aic.h>
12 #include <dt-bindings/interrupt-controller/irq.h>
13 #include <dt-bindings/pinctrl/apple.h>
16 	interrupt-parent = <&aic>;
17 	#address-cells = <2>;
18 	#size-cells = <2>;
20 	clkref: clock-ref {
21 		compatible = "fixed-clock";
22 		#clock-cells = <0>;
23 		clock-frequency = <24000000>;
24 		clock-output-names = "clkref";
28 		#address-cells = <2>;
29 		#size-cells = <0>;
31 		cpu0: cpu@0 {
34 			cpu-release-addr = <0 0>; /* To be filled in by loader */
35 			operating-points-v2 = <&twister_opp>;
36 			performance-domains = <&cpufreq>;
37 			enable-method = "spin-table";
38 			device_type = "cpu";
41 		cpu1: cpu@1 {
44 			cpu-release-addr = <0 0>; /* To be filled in by loader */
45 			operating-points-v2 = <&twister_opp>;
46 			performance-domains = <&cpufreq>;
47 			enable-method = "spin-table";
48 			device_type = "cpu";
52 	twister_opp: opp-table {
53 		compatible = "operating-points-v2";
56 			opp-hz = /bits/ 64 <300000000>;
57 			opp-level = <1>;
58 			clock-latency-ns = <800>;
61 			opp-hz = /bits/ 64 <396000000>;
62 			opp-level = <2>;
63 			clock-latency-ns = <53000>;
66 			opp-hz = /bits/ 64 <792000000>;
67 			opp-level = <3>;
68 			clock-latency-ns = <18000>;
71 			opp-hz = /bits/ 64 <1080000000>;
72 			opp-level = <4>;
73 			clock-latency-ns = <21000>;
76 			opp-hz = /bits/ 64 <1440000000>;
77 			opp-level = <5>;
78 			clock-latency-ns = <25000>;
81 			opp-hz = /bits/ 64 <1800000000>;
82 			opp-level = <6>;
83 			clock-latency-ns = <33000>;
86 			opp-hz = /bits/ 64 <2160000000>;
87 			opp-level = <7>;
88 			clock-latency-ns = <45000>;
91 		/* Not available until CPU deep sleep is implemented */
93 			opp-hz = /bits/ 64 <2160000000>;
94 			opp-level = <8>;
95 			clock-latency-ns = <45000>;
96 			turbo-mode;
102 		compatible = "simple-bus";
103 		#address-cells = <2>;
104 		#size-cells = <2>;
105 		nonposted-mmio;
108 		cpufreq: performance-controller@202220000 {
109 …compatible = "apple,s8000-cluster-cpufreq", "apple,t8103-cluster-cpufreq", "apple,cluster-cpufreq";
111 			#performance-domain-cells = <0>;
115 			compatible = "apple,s5l-uart";
117 			reg-io-width = <4>;
118 			interrupt-parent = <&aic>;
120 			/* Use the bootloader-enabled clocks for now. */
122 			clock-names = "uart", "clk_uart_baud0";
123 			power-domains = <&ps_uart0>;
127 		pmgr: power-management@20e000000 {
128 			compatible = "apple,s8000-pmgr", "apple,pmgr", "syscon", "simple-mfd";
129 			#address-cells = <1>;
130 			#size-cells = <1>;
135 		aic: interrupt-controller@20e100000 {
136 			compatible = "apple,s8000-aic", "apple,aic";
138 			#interrupt-cells = <3>;
139 			interrupt-controller;
140 			power-domains = <&ps_aic>;
144 			compatible = "apple,s8000-pinctrl", "apple,pinctrl";
146 			power-domains = <&ps_gpio>;
148 			gpio-controller;
149 			#gpio-cells = <2>;
150 			gpio-ranges = <&pinctrl_ap 0 0 219>;
153 			interrupt-controller;
154 			#interrupt-cells = <2>;
155 			interrupt-parent = <&aic>;
166 			compatible = "apple,s8000-pinctrl", "apple,pinctrl";
168 			power-domains = <&ps_aop_gpio>;
170 			gpio-controller;
171 			#gpio-cells = <2>;
172 			gpio-ranges = <&pinctrl_aop 0 0 28>;
175 			interrupt-controller;
176 			#interrupt-cells = <2>;
177 			interrupt-parent = <&aic>;
187 		pmgr_mini: power-management@210200000 {
188 			compatible = "apple,s8000-pmgr", "apple,pmgr", "syscon", "simple-mfd";
189 			#address-cells = <1>;
190 			#size-cells = <1>;
196 			compatible = "apple,s8000-wdt", "apple,wdt";
199 			interrupt-parent = <&aic>;
205 		compatible = "arm,armv8-timer";
206 		interrupt-parent = <&aic>;
207 		interrupt-names = "phys", "virt";
214 #include "s8001-pmgr.dtsi"