Lines Matching +full:trace +full:- +full:buffer +full:- +full:extension
1 # SPDX-License-Identifier: GPL-2.0-only
283 ARM 64-bit (AArch64) Linux support.
291 # required due to use of the -Zfixed-x18 flag.
294 # -Zsanitizer=shadow-call-stack flag.
304 depends on $(cc-option,-fpatchable-function-entry=2)
330 # VA_BITS - PTDESC_TABLE_SHIFT
408 def_bool !$(as-instr,1:\n.inst 0\n.rept . - 1b\n\nnop\n.endr\n)
413 # https://github.com/llvm/llvm-project/commit/2a96f47c5ffca84cd774ad402cacd137f4bf45e2
463 at stage-2.
471 …bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is acce…
476 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
479 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
485 data cache clean-and-invalidate.
493 …bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to th…
498 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
507 data cache clean-and-invalidate.
515 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
520 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
523 If a Cortex-A53 processor is executing a store or prefetch for
530 data cache clean-and-invalidate.
538 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
543 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
552 data cache clean-and-invalidate.
560 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
564 erratum 832075 on Cortex-A57 parts up to r1p2.
566 Affected Cortex-A57 parts might deadlock when exclusive load/store
567 instructions to Write-Back memory are mixed with Device loads.
569 The workaround is to promote device loads to use Load-Acquire
578 …bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a…
582 erratum 834220 on Cortex-A57 parts up to r1p2.
584 Affected Cortex-A57 parts might report a Stage 2 translation
598 …bool "Cortex-A57/A72: 1742098: ELR recorded incorrectly on interrupt taken between cryptographic i…
602 This option removes the AES hwcap for aarch32 user-space to
603 workaround erratum 1742098 on Cortex-A57 and Cortex-A72.
614 bool "Cortex-A53: 845719: a load might read incorrect data"
619 erratum 845719 on Cortex-A53 parts up to r0p4.
621 When running a compat (AArch32) userspace on an affected Cortex-A53
627 return to a 32-bit task.
635 bool "Cortex-A53: 843419: A load or store might access an incorrect address"
638 This option links the kernel with '--fix-cortex-a53-843419' and
641 Cortex-A53 parts up to r0p4.
646 def_bool $(ld-option,--fix-cortex-a53-843419)
649 …bool "Cortex-A55: 1024718: Update of DBM/AP bits without break before make might result in incorre…
652 This option adds a workaround for ARM Cortex-A55 Erratum 1024718.
654 Affected Cortex-A55 cores (all revisions) could cause incorrect
656 without a break-before-make. The workaround is to disable the usage
663 …bool "Cortex-A76/Neoverse-N1: MRC read following MRRC read of specific Generic Timer in AArch32 mi…
667 This option adds a workaround for ARM Cortex-A76/Neoverse-N1
670 Affected Cortex-A76/Neoverse-N1 cores (r0p0 to r3p1) could
680 …bool "Cortex-A76: 1165522: Speculative AT instruction using out-of-context translation regime coul…
684 This option adds a workaround for ARM Cortex-A76 erratum 1165522.
686 Affected Cortex-A76 cores (r0p0, r1p0, r2p0) could end-up with
693 …bool "Cortex-A57/A72: 1319537: Speculative AT instruction using out-of-context translation regime …
697 This option adds work arounds for ARM Cortex-A57 erratum 1319537
700 Cortex-A57 and A72 cores could end-up with corrupted TLBs by
706 …bool "Cortex-A55: 1530923: Speculative AT instruction using out-of-context translation regime coul…
710 This option adds a workaround for ARM Cortex-A55 erratum 1530923.
712 Affected Cortex-A55 cores (r0p0, r0p1, r1p0, r2p0) could end-up with
722 …bool "Cortex-A55: Completion of affected memory accesses might not be guaranteed by completion of …
725 This option adds a workaround for ARM Cortex-A55 erratum #2441007.
727 Under very rare circumstances, affected Cortex-A55 CPUs
728 may not handle a race between a break-before-make sequence on one
738 …bool "Cortex-A76: Modification of the translation table for a virtual address might lead to read-a…
741 This option adds a workaround for ARM Cortex-A76 erratum 1286807.
743 On the affected Cortex-A76 cores (r0p0 to r3p0), if a virtual
747 break-before-make sequence, then under very rare circumstances
755 bool "Cortex-A76: Software Step might prevent interrupt recognition"
758 This option adds a workaround for Arm Cortex-A76 erratum 1463225.
760 On the affected Cortex-A76 cores (r0p0 to r3p1), software stepping
773 bool "Neoverse-N1: workaround mis-ordering of instruction fetches (rare)"
775 This option adds a workaround for ARM Neoverse-N1 erratum
778 Affected Neoverse-N1 cores could execute a stale instruction when
783 forces user-space to perform cache maintenance.
788 …bool "Cortex-A77: 1508412: workaround deadlock on sequence of NC/Device load and store exclusive o…
791 This option adds a workaround for Arm Cortex-A77 erratum 1508412.
793 Affected Cortex-A77 cores (r0p0, r1p0) could deadlock on a sequence
794 of a store-exclusive or read of PAR_EL1 and a load with device or
795 non-cacheable memory attributes. The workaround depends on a firmware
811 bool "Cortex-A510: 2051678: disable Hardware Update of the page table dirty bit"
814 This options adds the workaround for ARM Cortex-A510 erratum ARM64_ERRATUM_2051678.
815 Affected Cortex-A510 might not respect the ordering rules for
822 bool "Cortex-A510: 2077057: workaround software-step corrupting SPSR_EL2"
825 This option adds the workaround for ARM Cortex-A510 erratum 2077057.
826 Affected Cortex-A510 may corrupt SPSR_EL2 when the a step exception is
834 previous guest entry, and can be restored from the in-memory copy.
839 bool "Cortex-A510: 2658417: remove BF16 support due to incorrect result"
842 This option adds the workaround for ARM Cortex-A510 erratum 2658417.
843 Affected Cortex-A510 (r0p0 to r1p1) may produce the wrong result for
847 user-space should not be using these instructions.
852 bool "Cortex-A710/X2: 2119858: workaround TRBE overwriting trace data in FILL mode"
857 This option adds the workaround for ARM Cortex-A710/X2 erratum 2119858.
859 Affected Cortex-A710/X2 cores could overwrite up to 3 cache lines of trace
860 data at the base of the buffer (pointed to by TRBASER_EL1) in FILL mode in
864 256 bytes before enabling the buffer and filling the first 256 bytes of
865 the buffer with ETM ignore packets upon disabling.
870 bool "Neoverse-N2: 2139208: workaround TRBE overwriting trace data in FILL mode"
875 This option adds the workaround for ARM Neoverse-N2 erratum 2139208.
877 Affected Neoverse-N2 cores could overwrite up to 3 cache lines of trace
878 data at the base of the buffer (pointed to by TRBASER_EL1) in FILL mode in
882 256 bytes before enabling the buffer and filling the first 256 bytes of
883 the buffer with ETM ignore packets upon disabling.
891 bool "Cortex-A710: 2054223: workaround TSB instruction failing to flush trace"
895 Enable workaround for ARM Cortex-A710 erratum 2054223
897 Affected cores may fail to flush the trace data on a TSB instruction, when
898 the PE is in trace prohibited state. This will cause losing a few bytes
899 of the trace cached.
906 bool "Neoverse-N2: 2067961: workaround TSB instruction failing to flush trace"
910 Enable workaround for ARM Neoverse-N2 erratum 2067961
912 Affected cores may fail to flush the trace data on a TSB instruction, when
913 the PE is in trace prohibited state. This will cause losing a few bytes
914 of the trace cached.
924 bool "Neoverse-N2: 2253138: workaround TRBE writing to address out-of-range"
929 This option adds the workaround for ARM Neoverse-N2 erratum 2253138.
931 Affected Neoverse-N2 cores might write to an out-of-range address, not reserved
942 bool "Cortex-A710/X2: 2224489: workaround TRBE writing to address out-of-range"
947 This option adds the workaround for ARM Cortex-A710/X2 erratum 2224489.
949 Affected Cortex-A710/X2 cores might write to an out-of-range address, not reserved
960 …bool "Cortex-A510: Completion of affected memory accesses might not be guaranteed by completion of…
963 This option adds a workaround for ARM Cortex-A510 erratum #2441009.
965 Under very rare circumstances, affected Cortex-A510 CPUs
966 may not handle a race between a break-before-make sequence on one
976 bool "Cortex-A510: 2064142: workaround TRBE register writes while disabled"
980 This option adds the workaround for ARM Cortex-A510 erratum 2064142.
982 Affected Cortex-A510 core might fail to write into system registers after the
994 bool "Cortex-A510: 2038923: workaround TRBE corruption with enable"
998 This option adds the workaround for ARM Cortex-A510 erratum 2038923.
1000 Affected Cortex-A510 core might cause an inconsistent view on whether trace is
1001 prohibited within the CPU. As a result, the trace buffer or trace buffer state
1002 might be corrupted. This happens after TRBE buffer has been enabled by setting
1004 execution changes from a context, in which trace is prohibited to one where it
1005 isn't, or vice versa. In these mentioned conditions, the view of whether trace
1006 is prohibited is inconsistent between parts of the CPU, and the trace buffer or
1007 the trace buffer state might be corrupted.
1010 trace is prohibited or not based on TRBLIMITR_EL1.E by immediately following a
1017 bool "Cortex-A510: 1902691: workaround TRBE trace corruption"
1021 This option adds the workaround for ARM Cortex-A510 erratum 1902691.
1023 Affected Cortex-A510 core might cause trace data corruption, when being written
1025 trace data.
1035 bool "Cortex-A510: 2457168: workaround for AMEVCNTR01 incrementing incorrectly"
1039 This option adds the workaround for ARM Cortex-A510 erratum 2457168.
1042 as the system counter. On affected Cortex-A510 cores AMEVCNTR01 increments
1052 bool "Cortex-A715: 2645198: Workaround possible [ESR|FAR]_ELx corruption"
1055 This option adds the workaround for ARM Cortex-A715 erratum 2645198.
1057 If a Cortex-A715 cpu sees a page mapping permissions change from executable
1058 to non-executable, it may corrupt the ESR_ELx and FAR_ELx registers on the
1061 Only user-space does executable to non-executable permission transition via
1062 mprotect() system call. Workaround the problem by doing a break-before-make
1071 bool "Cortex-A520: 2966298: workaround for speculatively executed unprivileged load"
1075 This option adds the workaround for ARM Cortex-A520 erratum 2966298.
1077 On an affected Cortex-A520 core, a speculatively executed unprivileged
1085 bool "Cortex-A510: 3117295: workaround for speculatively executed unprivileged load"
1089 This option adds the workaround for ARM Cortex-A510 erratum 3117295.
1091 On an affected Cortex-A510 core, a speculatively executed unprivileged
1099 bool "Cortex-*/Neoverse-*: workaround for MSR SSBS not self-synchronizing"
1104 * ARM Cortex-A76 erratum 3324349
1105 * ARM Cortex-A77 erratum 3324348
1106 * ARM Cortex-A78 erratum 3324344
1107 * ARM Cortex-A78C erratum 3324346
1108 * ARM Cortex-A78C erratum 3324347
1109 * ARM Cortex-A710 erratam 3324338
1110 * ARM Cortex-A715 errartum 3456084
1111 * ARM Cortex-A720 erratum 3456091
1112 * ARM Cortex-A725 erratum 3456106
1113 * ARM Cortex-X1 erratum 3324344
1114 * ARM Cortex-X1C erratum 3324346
1115 * ARM Cortex-X2 erratum 3324338
1116 * ARM Cortex-X3 erratum 3324335
1117 * ARM Cortex-X4 erratum 3194386
1118 * ARM Cortex-X925 erratum 3324334
1119 * ARM Neoverse-N1 erratum 3324349
1121 * ARM Neoverse-N3 erratum 3456111
1122 * ARM Neoverse-V1 erratum 3324341
1124 * ARM Neoverse-V3 erratum 3312417
1132 SSBS. The presence of the SSBS special-purpose register is hidden
1144 This implements two gicv3-its errata workarounds for ThunderX. Both
1184 contains data for a non-current ASID. The fix is to
1195 interrupts in host. Trapping both GICv3 group-0 and group-1
1218 bool "Fujitsu-A64FX erratum E#010001: Undefined fault may occur wrongly"
1221 This option adds a workaround for Fujitsu-A64FX erratum E#010001.
1222 On some variants of the Fujitsu-A64FX cores ver(1.0, 1.1), memory
1226 case-1 TTBR0_EL1 with TCR_EL1.NFD0 == 1.
1227 case-2 TTBR0_EL2 with TCR_EL2.NFD0 == 1.
1228 case-3 TTBR1_EL1 with TCR_EL1.NFD1 == 1.
1229 case-4 TTBR1_EL2 with TCR_EL2.NFD1 == 1.
1232 The workaround only affects the Fujitsu-A64FX.
1303 If CNP is enabled on Carmel cores, non-sharable TLBIs on a core will not
1322 The Rockchip RK3588 GIC600 SoC integration does not support ACE/ACE-lite.
1329 bool "Socionext Synquacer: Workaround for GICv3 pre-ITS"
1333 MSI doorbell writes with non-zero values for the device ID.
1365 look-up. AArch32 emulation requires applications compiled
1379 bool "36-bit" if EXPERT
1383 bool "39-bit"
1387 bool "42-bit"
1391 bool "47-bit"
1395 bool "48-bit"
1398 bool "52-bit"
1400 Enable 52-bit virtual addressing for userspace when explicitly
1401 requested via a hint to mmap(). The kernel will also use 52-bit
1403 this feature is available, otherwise it reverts to 48-bit).
1405 NOTE: Enabling 52-bit virtual addressing in conjunction with
1408 impact on its susceptibility to brute-force attacks.
1410 If unsure, select 48-bit virtual addressing instead.
1415 bool "Force 52-bit virtual addresses for userspace"
1418 For systems with 52-bit userspace VAs enabled, the kernel will attempt
1419 to maintain compatibility with older software by providing 48-bit VAs
1422 This configuration option disables the 48-bit compatibility logic, and
1423 forces all userspace addresses to be 52-bit on HW that supports it. One
1444 bool "48-bit"
1448 bool "52-bit"
1451 Enable support for a 52-bit physical address space, introduced as
1452 part of the ARMv8.2-LPA extension.
1455 do not support ARMv8.2-LPA, but with some added memory overhead (and
1478 bool "Build big-endian kernel"
1479 # https://github.com/llvm/llvm-project/commit/1379b150991f70a5782e9a143c2ba5308da1161c
1482 Say Y if you plan on running a kernel with a big-endian userspace.
1485 bool "Build little-endian kernel"
1487 Say Y if you plan on running a kernel with a little-endian userspace.
1493 bool "Multi-core scheduler support"
1495 Multi-core scheduler support improves the CPU scheduler's decision
1496 making when dealing with multi-core CPU chips at a cost of slightly
1505 by sharing mid-level caches, last-level cache tags or internal
1516 int "Maximum number of CPUs (2-4096)"
1521 bool "Support for hot-pluggable CPUs"
1537 Enable NUMA (Non-Uniform Memory Access) support.
1565 def_bool $(cc-option, -fsanitize=shadow-call-stack -ffixed-x18)
1634 # so the maximum value of MAX_PAGE_ORDER is SECTION_SIZE_BITS - PAGE_SHIFT:
1637 # ----+-------------------+--------------+----------------------+-------------------------+
1665 Speculation attacks against some high-performance processors can
1677 Speculation attacks against some high-performance processors can
1679 When taking an exception from user-space, a sequence of branches
1686 Apply read-only attributes of VM areas to the linear alias of
1687 the backing pages as well. This prevents code or read-only data
1702 user-space memory directly by pointing TTBR0_EL1 to a reserved
1713 Documentation/arch/arm64/tagged-address-abi.rst.
1716 bool "Kernel support for 32-bit EL0"
1722 This option enables support for a 32-bit EL0 running under a 64-bit
1723 kernel at EL1. AArch32-specific components such as system calls,
1731 If you want to execute 32-bit userspace applications, say Y.
1736 bool "Enable kuser helpers page for 32-bit applications"
1739 Warning: disabling this option may break 32-bit user programs.
1763 bool "Enable vDSO for 32-bit applications"
1769 Place in the process address space of 32-bit applications an
1773 You must have a 32-bit build of glibc 2.22 or later for programs
1777 bool "Compile the 32-bit vDSO for Thumb-2 mode" if EXPERT
1781 Compile the compat vDSO with '-mthumb -fomit-frame-pointer' if y,
1782 otherwise with '-marm'.
1785 bool "Fix up misaligned multi-word loads and stores in user space"
1827 The CP15 barrier instructions - CP15ISB, CP15DSB, and
1828 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
1843 The SETEND instruction alters the data-endianness of the
1851 for this feature to be enabled. If a new CPU - which doesn't support mixed
1852 endian - is hotplugged in after this feature has been enabled, there could
1871 Similarly, writes to read-only pages with the DBM bit set will
1872 clear the read-only bit (AP[2]) instead of raising a
1876 to work on pre-ARMv8.1 hardware and the performance impact is
1884 prevents the kernel or hypervisor from accessing user-space (EL0)
1894 def_bool $(as-instr,.arch_extension lse)
1909 Say Y here to make use of these instructions for the in-kernel
1920 def_bool $(cc-option,-Wa$(comma)-march=armv8.2-a)
1923 def_bool $(as-instr,.arch armv8.2-a+sha3)
1950 and access the new registers if the system supports the extension.
1982 context-switched along with the process.
2005 If the compiler supports the -mbranch-protection or
2006 -msign-return-address flag (e.g. GCC 7 or later), then this option
2017 def_bool $(cc-option,-mbranch-protection=pac-ret+leaf)
2021 def_bool $(cc-option,-msign-return-address=all)
2024 def_bool $(cc-option,-Wa$(comma)-march=armv8.3-a)
2027 def_bool $(as-instr,.cfi_startproc\n.cfi_negate_ra_state\n.cfi_endproc\n)
2030 def_bool $(as-instr,.arch_extension rcpc)
2037 bool "Enable support for the Activity Monitors Unit CPU extension"
2040 The activity monitors extension is an optional extension introduced
2044 To enable the use of this extension on CPUs that implement it, say Y.
2048 extension. The required support is present in:
2060 def_bool $(cc-option,-Wa$(comma)-march=armv8.4-a)
2067 ARMv8.4-TLBI provides TLBI invalidation instruction that apply to a
2078 def_bool $(cc-option,-Wa$(comma)-march=armv8.5-a)
2121 def_bool $(cc-option,-mbranch-protection=pac-ret+leaf+bti)
2137 # ".arch armv8.5-a+memtag" below. However, this was incomplete
2141 def_bool $(as-instr,.arch armv8.5-a+memtag\nstgm xzr$(comma)[x0])
2144 bool "Memory Tagging Extension support"
2157 architectural support for run-time, always-on detection of
2159 to eliminate vulnerabilities arising from memory-unsafe
2163 Extension at EL0 (i.e. for userspace).
2167 not be allowed a late bring-up.
2173 Documentation/arch/arm64/memory-tagging-extension.rst.
2185 Access Never to be used with Execute-only mappings.
2192 def_bool $(as-instr,.arch_extension mops)
2197 prompt "Permission Overlay Extension"
2202 The Permission Overlay Extension is used to implement Memory
2204 enforcing page-based protections, but without requiring modification
2207 For details, see Documentation/core-api/protection-keys.rst
2254 bool "ARM Scalable Vector Extension support"
2257 The Scalable Vector Extension (SVE) is an extension to the AArch64
2262 To enable use of this extension on CPUs that implement it, say Y.
2278 If you need the kernel to boot on SVE-capable hardware with broken
2285 bool "ARM Scalable Matrix Extension support"
2290 The Scalable Matrix Extension (SME) is an extension to the AArch64
2297 bool "Support for NMI-like interrupts"
2300 Adds support for mimicking Non-Maskable Interrupts through the use of
2343 random u64 value in /chosen/kaslr-seed at kernel entry.
2370 …def_bool $(cc-option,-mstack-protector-guard=sysreg -mstack-protector-guard-reg=sp_el0 -mstack-pro…
2378 …# needs Clang with https://github.com/llvm/llvm-project/commit/de07cde67b5d205d58690be012106022aea…
2411 Provide a set of default command-line options at build time by
2426 Uses the command-line options passed by the boot loader. If
2436 command-line options your boot loader passes to the kernel.
2458 by UEFI firmware (such as non-volatile variables, realtime
2483 continue to boot on existing non-UEFI platforms.