Lines Matching +full:in +full:- +full:and +full:- +full:around
1 # SPDX-License-Identifier: GPL-2.0-only
283 ARM 64-bit (AArch64) Linux support.
291 # required due to use of the -Zfixed-x18 flag.
294 # -Zsanitizer=shadow-call-stack flag.
304 depends on $(cc-option,-fpatchable-function-entry=2)
330 # VA_BITS - PTDESC_TABLE_SHIFT
408 def_bool !$(as-instr,1:\n.inst 0\n.rept . - 1b\n\nnop\n.endr\n)
413 # https://github.com/llvm/llvm-project/commit/2a96f47c5ffca84cd774ad402cacd137f4bf45e2
416 # and this was backported to 10.2.0, 9.4.0, 8.5.0, but not earlier
449 …bool "AmpereOne: AC03_CPU_38: Certain bits in the Virtualization Translation Control Register and …
452 This option adds an alternative code sequence to work around Ampere
453 errata AC03_CPU_38 and AC04_CPU_10 on AmpereOne.
455 The affected design reports FEAT_HAFDBS as not implemented in
463 at stage-2.
471 …bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is acce…
475 This option adds an alternative code sequence to work around ARM
476 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
477 AXI master interface and an L2 cache.
479 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
480 and is unable to accept a certain write via this interface, it will
481 not progress on read data presented on the read data channel and the
485 data cache clean-and-invalidate.
493 …bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to th…
497 This option adds an alternative code sequence to work around ARM
498 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
499 master interface and an L2 cache.
507 data cache clean-and-invalidate.
515 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
519 This option adds an alternative code sequence to work around ARM
520 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
523 If a Cortex-A53 processor is executing a store or prefetch for
524 write instruction at the same time as a processor in another
530 data cache clean-and-invalidate.
538 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
542 This option adds an alternative code sequence to work around ARM
543 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
546 If the processor is executing a load and store exclusive sequence at
547 the same time as a processor in another cluster is executing a cache
552 data cache clean-and-invalidate.
560 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
563 This option adds an alternative code sequence to work around ARM
564 erratum 832075 on Cortex-A57 parts up to r1p2.
566 Affected Cortex-A57 parts might deadlock when exclusive load/store
567 instructions to Write-Back memory are mixed with Device loads.
569 The workaround is to promote device loads to use Load-Acquire
578 …bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a…
581 This option adds an alternative code sequence to work around ARM
582 erratum 834220 on Cortex-A57 parts up to r1p2.
584 Affected Cortex-A57 parts might report a Stage 2 translation
587 alignment fault at Stage 1 and a translation fault at Stage 2.
598 …bool "Cortex-A57/A72: 1742098: ELR recorded incorrectly on interrupt taken between cryptographic i…
602 This option removes the AES hwcap for aarch32 user-space to
603 workaround erratum 1742098 on Cortex-A57 and Cortex-A72.
614 bool "Cortex-A53: 845719: a load might read incorrect data"
618 This option adds an alternative code sequence to work around ARM
619 erratum 845719 on Cortex-A53 parts up to r0p4.
621 When running a compat (AArch32) userspace on an affected Cortex-A53
627 return to a 32-bit task.
635 bool "Cortex-A53: 843419: A load or store might access an incorrect address"
638 This option links the kernel with '--fix-cortex-a53-843419' and
641 Cortex-A53 parts up to r0p4.
646 def_bool $(ld-option,--fix-cortex-a53-843419)
649 …bool "Cortex-A55: 1024718: Update of DBM/AP bits without break before make might result in incorre…
652 This option adds a workaround for ARM Cortex-A55 Erratum 1024718.
654 Affected Cortex-A55 cores (all revisions) could cause incorrect
656 without a break-before-make. The workaround is to disable the usage
663 …bool "Cortex-A76/Neoverse-N1: MRC read following MRRC read of specific Generic Timer in AArch32 mi…
667 This option adds a workaround for ARM Cortex-A76/Neoverse-N1
668 errata 1188873 and 1418040.
670 Affected Cortex-A76/Neoverse-N1 cores (r0p0 to r3p1) could
680 …bool "Cortex-A76: 1165522: Speculative AT instruction using out-of-context translation regime coul…
684 This option adds a workaround for ARM Cortex-A76 erratum 1165522.
686 Affected Cortex-A76 cores (r0p0, r1p0, r2p0) could end-up with
693 …bool "Cortex-A57/A72: 1319537: Speculative AT instruction using out-of-context translation regime …
697 This option adds work arounds for ARM Cortex-A57 erratum 1319537
698 and A72 erratum 1319367
700 Cortex-A57 and A72 cores could end-up with corrupted TLBs by
706 …bool "Cortex-A55: 1530923: Speculative AT instruction using out-of-context translation regime coul…
710 This option adds a workaround for ARM Cortex-A55 erratum 1530923.
712 Affected Cortex-A55 cores (r0p0, r0p1, r1p0, r2p0) could end-up with
722 …bool "Cortex-A55: Completion of affected memory accesses might not be guaranteed by completion of …
725 This option adds a workaround for ARM Cortex-A55 erratum #2441007.
727 Under very rare circumstances, affected Cortex-A55 CPUs
728 may not handle a race between a break-before-make sequence on one
729 CPU, and another CPU accessing the same page. This could allow a
732 Work around this by adding the affected CPUs to the list that needs
738 …bool "Cortex-A76: Modification of the translation table for a virtual address might lead to read-a…
741 This option adds a workaround for ARM Cortex-A76 erratum 1286807.
743 On the affected Cortex-A76 cores (r0p0 to r3p0), if a virtual
747 break-before-make sequence, then under very rare circumstances
755 bool "Cortex-A76: Software Step might prevent interrupt recognition"
758 This option adds a workaround for Arm Cortex-A76 erratum 1463225.
760 On the affected Cortex-A76 cores (r0p0 to r3p1), software stepping
762 subsequent interrupts when software stepping is disabled in the
763 exception handler of the system call and either kernel debugging
764 is enabled or VHE is in use.
766 Work around the erratum by triggering a dummy step exception
768 in a VHE configuration of the kernel.
773 bool "Neoverse-N1: workaround mis-ordering of instruction fetches (rare)"
775 This option adds a workaround for ARM Neoverse-N1 erratum
778 Affected Neoverse-N1 cores could execute a stale instruction when
783 forces user-space to perform cache maintenance.
788 …bool "Cortex-A77: 1508412: workaround deadlock on sequence of NC/Device load and store exclusive o…
791 This option adds a workaround for Arm Cortex-A77 erratum 1508412.
793 Affected Cortex-A77 cores (r0p0, r1p0) could deadlock on a sequence
794 of a store-exclusive or read of PAR_EL1 and a load with device or
795 non-cacheable memory attributes. The workaround depends on a firmware
801 Work around the issue by inserting DMB SY barriers around PAR_EL1
802 register reads and warning KVM users. The DMB barrier is sufficient
811 bool "Cortex-A510: 2051678: disable Hardware Update of the page table dirty bit"
814 This options adds the workaround for ARM Cortex-A510 erratum ARM64_ERRATUM_2051678.
815 Affected Cortex-A510 might not respect the ordering rules for
822 bool "Cortex-A510: 2077057: workaround software-step corrupting SPSR_EL2"
825 This option adds the workaround for ARM Cortex-A510 erratum 2077057.
826 Affected Cortex-A510 may corrupt SPSR_EL2 when the a step exception is
834 previous guest entry, and can be restored from the in-memory copy.
839 bool "Cortex-A510: 2658417: remove BF16 support due to incorrect result"
842 This option adds the workaround for ARM Cortex-A510 erratum 2658417.
843 Affected Cortex-A510 (r0p0 to r1p1) may produce the wrong result for
844 BFMMLA or VMMLA instructions in rare circumstances when a pair of
847 user-space should not be using these instructions.
852 bool "Cortex-A710/X2: 2119858: workaround TRBE overwriting trace data in FILL mode"
857 This option adds the workaround for ARM Cortex-A710/X2 erratum 2119858.
859 Affected Cortex-A710/X2 cores could overwrite up to 3 cache lines of trace
860 data at the base of the buffer (pointed to by TRBASER_EL1) in FILL mode in
863 Work around the issue by always making sure we move the TRBPTR_EL1 by
864 256 bytes before enabling the buffer and filling the first 256 bytes of
870 bool "Neoverse-N2: 2139208: workaround TRBE overwriting trace data in FILL mode"
875 This option adds the workaround for ARM Neoverse-N2 erratum 2139208.
877 Affected Neoverse-N2 cores could overwrite up to 3 cache lines of trace
878 data at the base of the buffer (pointed to by TRBASER_EL1) in FILL mode in
881 Work around the issue by always making sure we move the TRBPTR_EL1 by
882 256 bytes before enabling the buffer and filling the first 256 bytes of
891 bool "Cortex-A710: 2054223: workaround TSB instruction failing to flush trace"
895 Enable workaround for ARM Cortex-A710 erratum 2054223
898 the PE is in trace prohibited state. This will cause losing a few bytes
906 bool "Neoverse-N2: 2067961: workaround TSB instruction failing to flush trace"
910 Enable workaround for ARM Neoverse-N2 erratum 2067961
913 the PE is in trace prohibited state. This will cause losing a few bytes
924 bool "Neoverse-N2: 2253138: workaround TRBE writing to address out-of-range"
929 This option adds the workaround for ARM Neoverse-N2 erratum 2253138.
931 Affected Neoverse-N2 cores might write to an out-of-range address, not reserved
934 (i.e., the TRBLIMITR_EL1.LIMIT), instead of wrapping around to the base.
936 Work around this in the driver by always making sure that there is a
942 bool "Cortex-A710/X2: 2224489: workaround TRBE writing to address out-of-range"
947 This option adds the workaround for ARM Cortex-A710/X2 erratum 2224489.
949 Affected Cortex-A710/X2 cores might write to an out-of-range address, not reserved
952 (i.e., the TRBLIMITR_EL1.LIMIT), instead of wrapping around to the base.
954 Work around this in the driver by always making sure that there is a
960 …bool "Cortex-A510: Completion of affected memory accesses might not be guaranteed by completion of…
963 This option adds a workaround for ARM Cortex-A510 erratum #2441009.
965 Under very rare circumstances, affected Cortex-A510 CPUs
966 may not handle a race between a break-before-make sequence on one
967 CPU, and another CPU accessing the same page. This could allow a
970 Work around this by adding the affected CPUs to the list that needs
976 bool "Cortex-A510: 2064142: workaround TRBE register writes while disabled"
980 This option adds the workaround for ARM Cortex-A510 erratum 2064142.
982 Affected Cortex-A510 core might fail to write into system registers after the
985 and TRBTRG_EL1 will be ignored and will not be effected.
987 Work around this in the driver by executing TSB CSYNC and DSB after collection
988 is stopped and before performing a system register write to one of the affected
994 bool "Cortex-A510: 2038923: workaround TRBE corruption with enable"
998 This option adds the workaround for ARM Cortex-A510 erratum 2038923.
1000 Affected Cortex-A510 core might cause an inconsistent view on whether trace is
1004 execution changes from a context, in which trace is prohibited to one where it
1005 isn't, or vice versa. In these mentioned conditions, the view of whether trace
1006 is prohibited is inconsistent between parts of the CPU, and the trace buffer or
1009 Work around this in the driver by preventing an inconsistent view of whether the
1017 bool "Cortex-A510: 1902691: workaround TRBE trace corruption"
1021 This option adds the workaround for ARM Cortex-A510 erratum 1902691.
1023 Affected Cortex-A510 core might cause trace data corruption, when being written
1024 into the memory. Effectively TRBE is broken and hence cannot be used to capture
1027 Work around this problem in the driver by just preventing TRBE initialization on
1035 bool "Cortex-A510: 2457168: workaround for AMEVCNTR01 incrementing incorrectly"
1039 This option adds the workaround for ARM Cortex-A510 erratum 2457168.
1042 as the system counter. On affected Cortex-A510 cores AMEVCNTR01 increments
1045 Work around this problem by returning 0 when reading the affected counter in
1046 key locations that results in disabling all users of this counter. This effect
1052 bool "Cortex-A715: 2645198: Workaround possible [ESR|FAR]_ELx corruption"
1055 This option adds the workaround for ARM Cortex-A715 erratum 2645198.
1057 If a Cortex-A715 cpu sees a page mapping permissions change from executable
1058 to non-executable, it may corrupt the ESR_ELx and FAR_ELx registers on the
1061 Only user-space does executable to non-executable permission transition via
1062 mprotect() system call. Workaround the problem by doing a break-before-make
1071 bool "Cortex-A520: 2966298: workaround for speculatively executed unprivileged load"
1075 This option adds the workaround for ARM Cortex-A520 erratum 2966298.
1077 On an affected Cortex-A520 core, a speculatively executed unprivileged
1080 Work around this problem by executing a TLBI before returning to EL0.
1085 bool "Cortex-A510: 3117295: workaround for speculatively executed unprivileged load"
1089 This option adds the workaround for ARM Cortex-A510 erratum 3117295.
1091 On an affected Cortex-A510 core, a speculatively executed unprivileged
1094 Work around this problem by executing a TLBI before returning to EL0.
1099 bool "Cortex-*/Neoverse-*: workaround for MSR SSBS not self-synchronizing"
1104 * ARM Cortex-A76 erratum 3324349
1105 * ARM Cortex-A77 erratum 3324348
1106 * ARM Cortex-A78 erratum 3324344
1107 * ARM Cortex-A78C erratum 3324346
1108 * ARM Cortex-A78C erratum 3324347
1109 * ARM Cortex-A710 erratam 3324338
1110 * ARM Cortex-A715 errartum 3456084
1111 * ARM Cortex-A720 erratum 3456091
1112 * ARM Cortex-A725 erratum 3456106
1113 * ARM Cortex-X1 erratum 3324344
1114 * ARM Cortex-X1C erratum 3324346
1115 * ARM Cortex-X2 erratum 3324338
1116 * ARM Cortex-X3 erratum 3324335
1117 * ARM Cortex-X4 erratum 3194386
1118 * ARM Cortex-X925 erratum 3324334
1119 * ARM Neoverse-N1 erratum 3324349
1121 * ARM Neoverse-N3 erratum 3456111
1122 * ARM Neoverse-V1 erratum 3324341
1124 * ARM Neoverse-V3 erratum 3312417
1130 Work around this problem by placing a Speculation Barrier (SB) or
1132 SSBS. The presence of the SSBS special-purpose register is hidden
1133 from hwcaps and EL0 reads of ID_AA64PFR1_EL1, such that userspace
1142 Enable workaround for errata 22375 and 24313.
1144 This implements two gicv3-its errata workarounds for ThunderX. Both
1150 The fixes are in ITS initialization and basically ignore memory access
1151 type and table size provided by the TYPER and BASER registers.
1160 ITS SYNC command hang for cross node io and collections/cpu mapping.
1165 bool "Cavium errata 23154 and 38545: GICv3 lacks HW synchronisation"
1170 (access to icc_iar1_el1 is not sync'ed before and after).
1173 OcteonTX and OcteonTX2), resulting in deactivated interrupts being
1184 contains data for a non-current ASID. The fix is to
1190 bool "Cavium erratum 30115: Guest may disable interrupts in host"
1194 1.2, and T83 Pass 1.0, KVM guest execution may disable
1195 interrupts in host. Trapping both GICv3 group-0 and group-1
1201 bool "Cavium ThunderX2 erratum 219: PRFM between TTBR change and ISB fails"
1205 TTBR update and the corresponding context synchronizing operation can
1206 cause a spurious Data Abort to be delivered to any hardware thread in
1209 Work around the issue by avoiding the problematic code sequence and
1212 instruction and ensures context synchronization by virtue of the
1218 bool "Fujitsu-A64FX erratum E#010001: Undefined fault may occur wrongly"
1221 This option adds a workaround for Fujitsu-A64FX erratum E#010001.
1222 On some variants of the Fujitsu-A64FX cores ver(1.0, 1.1), memory
1226 case-1 TTBR0_EL1 with TCR_EL1.NFD0 == 1.
1227 case-2 TTBR0_EL2 with TCR_EL2.NFD0 == 1.
1228 case-3 TTBR1_EL1 with TCR_EL1.NFD1 == 1.
1229 case-4 TTBR1_EL2 with TCR_EL2.NFD1 == 1.
1231 The workaround is to ensure these bits are clear in TCR_ELx.
1232 The workaround only affects the Fujitsu-A64FX.
1241 when issued ITS commands such as VMOVP and VMAPP, and requires
1242 a 128kB offset to be applied to the target address in this commands.
1250 When enabling GICv4.1 in hip09, VMAPP will fail to clear some caches
1261 On Falkor v1, an incorrect ASID may be cached in the TLB when ASID
1262 and BADDR are changed together in TTBRx_EL1. Since we keep the ASID
1263 in TTBR1_EL1, this situation only occurs in the entry trampoline and
1264 then only for entries in the walk cache, since the leaf translation
1265 is unchanged. Work around the erratum by invalidating the walk cache
1303 If CNP is enabled on Carmel cores, non-sharable TLBIs on a core will not
1313 The Rockchip RK3566 and RK3568 GIC600 SoC integrations have AXI
1322 The Rockchip RK3588 GIC600 SoC integration does not support ACE/ACE-lite.
1329 bool "Socionext Synquacer: Workaround for GICv3 pre-ITS"
1333 MSI doorbell writes with non-zero values for the device ID.
1364 allowing only two levels of page tables and faster TLB
1365 look-up. AArch32 emulation requires applications compiled
1376 a combination of page size and virtual address space size.
1379 bool "36-bit" if EXPERT
1383 bool "39-bit"
1387 bool "42-bit"
1391 bool "47-bit"
1395 bool "48-bit"
1398 bool "52-bit"
1400 Enable 52-bit virtual addressing for userspace when explicitly
1401 requested via a hint to mmap(). The kernel will also use 52-bit
1403 this feature is available, otherwise it reverts to 48-bit).
1405 NOTE: Enabling 52-bit virtual addressing in conjunction with
1406 ARMv8.3 Pointer Authentication will result in the PAC being
1408 impact on its susceptibility to brute-force attacks.
1410 If unsure, select 48-bit virtual addressing instead.
1415 bool "Force 52-bit virtual addresses for userspace"
1418 For systems with 52-bit userspace VAs enabled, the kernel will attempt
1419 to maintain compatibility with older software by providing 48-bit VAs
1422 This configuration option disables the 48-bit compatibility logic, and
1423 forces all userspace addresses to be 52-bit on HW that supports it. One
1444 bool "48-bit"
1448 bool "52-bit"
1451 Enable support for a 52-bit physical address space, introduced as
1452 part of the ARMv8.2-LPA extension.
1455 do not support ARMv8.2-LPA, but with some added memory overhead (and
1474 applications will need to be compiled and linked for the endianness
1478 bool "Build big-endian kernel"
1479 # https://github.com/llvm/llvm-project/commit/1379b150991f70a5782e9a143c2ba5308da1161c
1482 Say Y if you plan on running a kernel with a big-endian userspace.
1485 bool "Build little-endian kernel"
1487 Say Y if you plan on running a kernel with a little-endian userspace.
1493 bool "Multi-core scheduler support"
1495 Multi-core scheduler support improves the CPU scheduler's decision
1496 making when dealing with multi-core CPU chips at a cost of slightly
1497 increased overhead in some places. If unsure say N here.
1505 by sharing mid-level caches, last-level cache tags or internal
1512 MultiThreading at a cost of slightly increased overhead in some
1516 int "Maximum number of CPUs (2-4096)"
1521 bool "Support for hot-pluggable CPUs"
1524 Say Y here to experiment with turning CPUs off and on. CPUs
1529 bool "NUMA Memory Allocation and Scheduler Support"
1537 Enable NUMA (Non-Uniform Memory Access) support.
1540 local memory of the CPU and add some more
1565 def_bool $(cc-option, -fsanitize=shadow-call-stack -ffixed-x18)
1579 accounting. Time spent executing other tasks in parallel with
1583 If in doubt, say N here.
1628 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.
1634 # so the maximum value of MAX_PAGE_ORDER is SECTION_SIZE_BITS - PAGE_SHIFT:
1637 # ----+-------------------+--------------+----------------------+-------------------------+
1648 contiguous allocations. The limit is called MAX_PAGE_ORDER and it
1662 bool "Unmap kernel when running in userspace (KPTI)" if EXPERT
1665 Speculation attacks against some high-performance processors can
1666 be used to bypass MMU permission checks and leak kernel data to
1668 when running in userspace, mapping it back in on exception entry
1669 via a trampoline page in the vector table.
1677 Speculation attacks against some high-performance processors can
1679 When taking an exception from user-space, a sequence of branches
1686 Apply read-only attributes of VM areas to the linear alias of
1687 the backing pages as well. This prevents code or read-only data
1690 be turned off at runtime by passing rodata=[off|on] (and turned on
1694 which may adversely affect performance in some cases.
1702 user-space memory directly by pointing TTBR0_EL1 to a reserved
1703 zeroed area and reserved ASID. The user access routines
1710 When this option is enabled, user applications can opt in to a
1713 Documentation/arch/arm64/tagged-address-abi.rst.
1716 bool "Kernel support for 32-bit EL0"
1722 This option enables support for a 32-bit EL0 running under a 64-bit
1723 kernel at EL1. AArch32-specific components such as system calls,
1724 the user helper functions, VFP support and the ptrace interface are
1731 If you want to execute 32-bit userspace applications, say Y.
1736 bool "Enable kuser helpers page for 32-bit applications"
1739 Warning: disabling this option may break 32-bit user programs.
1742 helper code to userspace in read only form at a fixed location
1753 If all of the binaries and libraries which run on your platform
1754 are built specifically for your platform, and make no use of
1756 such exploits. However, in that case, if a binary or library
1763 bool "Enable vDSO for 32-bit applications"
1769 Place in the process address space of 32-bit applications an
1771 and clock_gettime.
1773 You must have a 32-bit build of glibc 2.22 or later for programs
1777 bool "Compile the 32-bit vDSO for Thumb-2 mode" if EXPERT
1781 Compile the compat vDSO with '-mthumb -fomit-frame-pointer' if y,
1782 otherwise with '-marm'.
1785 bool "Fix up misaligned multi-word loads and stores in user space"
1792 that have been deprecated or obsoleted in the architecture.
1810 In some older versions of glibc [<=2.8] SWP is used during futex
1827 The CP15 barrier instructions - CP15ISB, CP15DSB, and
1828 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
1829 strongly recommended to use the ISB, DSB, and DMB
1843 The SETEND instruction alters the data-endianness of the
1844 AArch32 EL0, and is deprecated in ARMv8.
1851 for this feature to be enabled. If a new CPU - which doesn't support mixed
1852 endian - is hotplugged in after this feature has been enabled, there could
1853 be unexpected results in the applications.
1863 bool "Support for hardware updates of the Access and Dirty page flags"
1867 hardware updates of the access and dirty information in page
1868 table entries. When enabled in TCR_EL1 (HA and HD bits) on
1871 Similarly, writes to read-only pages with the DBM bit set will
1872 clear the read-only bit (AP[2]) instead of raising a
1876 to work on pre-ARMv8.1 hardware and the performance impact is
1884 prevents the kernel or hypervisor from accessing user-space (EL0)
1890 The feature is detected at runtime, and will remain as a 'nop'
1894 def_bool $(as-instr,.arch_extension lse)
1906 atomic instructions that are designed specifically to scale in
1909 Say Y here to make use of these instructions for the in-kernel
1911 not support these instructions and requires the kernel to be
1912 built with binutils >= 2.25 in order for the new instructions
1920 def_bool $(cc-option,-Wa$(comma)-march=armv8.2-a)
1923 def_bool $(as-instr,.arch armv8.2-a+sha3)
1933 The feature is detected at runtime, and the kernel will use DC CVAC
1941 CPUs that support the Reliability, Availability and Serviceability
1942 (RAS) Extensions, part of ARMv8.2 are able to track faults and
1943 errors, classify them and report them to software.
1946 barriers to determine if faults are pending and read the
1950 and access the new registers if the system supports the extension.
1958 be shared between different PEs in the same inner shareable
1960 caching of such entries in the TLB.
1963 at runtime, and does not affect PEs that do not implement
1975 instructions for signing and authenticating pointers against secret
1977 and other attacks.
1982 context-switched along with the process.
1984 The feature is detected at runtime. If the feature is not present in
1990 address auth and the late CPU has then the late CPU will still boot
2005 If the compiler supports the -mbranch-protection or
2006 -msign-return-address flag (e.g. GCC 7 or later), then this option
2008 protection. In this case, and if the target hardware is known to
2017 def_bool $(cc-option,-mbranch-protection=pac-ret+leaf)
2021 def_bool $(cc-option,-msign-return-address=all)
2024 def_bool $(cc-option,-Wa$(comma)-march=armv8.3-a)
2027 def_bool $(as-instr,.cfi_startproc\n.cfi_negate_ra_state\n.cfi_endproc\n)
2030 def_bool $(as-instr,.arch_extension rcpc)
2048 extension. The required support is present in:
2049 * Version 1.5 and later of the ARM Trusted Firmware
2060 def_bool $(cc-option,-Wa$(comma)-march=armv8.4-a)
2067 ARMv8.4-TLBI provides TLBI invalidation instruction that apply to a
2070 The feature introduces new assembly instructions, and they were
2078 def_bool $(cc-option,-Wa$(comma)-march=armv8.5-a)
2115 and enable enforcement of this for kernel code. When this option
2116 is enabled and the system supports BTI all kernel code including
2121 def_bool $(cc-option,-mbranch-protection=pac-ret+leaf+bti)
2128 that EL0 accesses made via TTBR1 always fault in constant time,
2130 with lower overhead and without disrupting legitimate access to
2136 # Initial support for MTE went in binutils 2.32.0, checked with
2137 # ".arch armv8.5-a+memtag" below. However, this was incomplete
2139 # is only supported in the newer 2.32.x and 2.33 binutils
2141 def_bool $(as-instr,.arch armv8.5-a+memtag\nstgm xzr$(comma)[x0])
2149 # Required for tag checking in the uaccess routines
2157 architectural support for run-time, always-on detection of
2159 to eliminate vulnerabilities arising from memory-unsafe
2167 not be allowed a late bring-up.
2170 explicitly opt in. The mechanism for the userspace is
2171 described in:
2173 Documentation/arch/arm64/memory-tagging-extension.rst.
2185 Access Never to be used with Execute-only mappings.
2187 The feature is detected at runtime, and will remain disabled
2192 def_bool $(as-instr,.arch_extension mops)
2204 enforcing page-based protections, but without requiring modification
2207 For details, see Documentation/core-api/protection-keys.rst
2222 memory access will update the Access Flag in each Table descriptor
2223 which is accessed during the translation table walk and for which
2227 The feature will only be enabled if all the CPUs in the system
2245 stored in the GCS, and may also be used to efficiently obtain
2248 The feature is detected at runtime, and will remain disabled
2258 execution state which complements and extends the SIMD functionality
2259 of the base architecture to support much larger vectors and to enable
2269 is present in:
2271 * version 1.5 and later of the ARM Trusted Firmware
2273 ("bootwrapper: SVE: Enable SVE for EL2 and below").
2278 If you need the kernel to boot on SVE-capable hardware with broken
2281 booting the kernel. If unsure and you are not observing these
2297 bool "Support for NMI-like interrupts"
2300 Adds support for mimicking Non-Maskable Interrupts through the use of
2343 random u64 value in /chosen/kaslr-seed at kernel entry.
2347 to the kernel proper. In addition, it will randomise the physical
2360 but it does imply that function calls between modules and the core
2361 kernel will need to be resolved via veneers in the module PLT.
2365 core kernel, so branch relocations are almost always in range unless
2366 the region is exhausted. In this particular case of region
2370 …def_bool $(cc-option,-mstack-protector-guard=sysreg -mstack-protector-guard-reg=sp_el0 -mstack-pro…
2378 …# needs Clang with https://github.com/llvm/llvm-project/commit/de07cde67b5d205d58690be012106022aea…
2391 bit, for any mappings that meet the size and alignment requirements.
2392 This reduces TLB pressure and improves performance.
2404 protocol even if the corresponding data is present in the ACPI
2411 Provide a set of default command-line options at build time by
2426 Uses the command-line options passed by the boot loader. If
2428 string provided in CMDLINE will be used.
2436 command-line options your boot loader passes to the kernel.
2458 by UEFI firmware (such as non-volatile variables, realtime
2459 clock, and platform reset). A UEFI stub is also provided to
2470 "make zinstall" first, and verifying that everything is fine
2471 in your environment before making "make install" do this for
2483 continue to boot on existing non-UEFI platforms.