arm/mm/proc-sa1100.S

1 /* SPDX-License-Identifier: GPL-2.0-only */
3  *  linux/arch/arm/mm/proc-sa1100.S
5  *  Copyright (C) 1997-2002 Russell King
6  *  hacked for non-paged-MM by Hyok S. Choi, 2003.
11  *  functions on the StrongARM-1100 and StrongARM-1110.
15  *  12-jun-2000, Erik Mouw (J.A.K.Mouw@its.tudelft.nl):
23 #include <asm/asm-offsets.h>
26 #include <asm/pgtable-hwdef.h>
28 #include "proc-macros.S"
43 	mcr	p15, 0, r0, c9, c0, 5		@ Allow read-buffer operations from userland
51  *  - Disable interrupts
52  *  - Clean and turn off caches.
55 	mcr	p15, 0, ip, c15, c2, 2		@ Disable clock switching
66  * Perform a soft reset of the system.  Put the CPU into the
70  * loc: location to jump to for soft reset
75 	mov	ip, #0
76 	mcr	p15, 0, ip, c7, c7, 0		@ invalidate I,D caches
77 	mcr	p15, 0, ip, c7, c10, 4		@ drain WB
79 	mcr	p15, 0, ip, c8, c7, 0		@ invalidate I & D TLBs
81 	mrc	p15, 0, ip, c1, c0, 0		@ ctrl register
82 	bic	ip, ip, #0x000f			@ ............wcam
83 	bic	ip, ip, #0x1100			@ ...i...s........
84 	mcr	p15, 0, ip, c1, c0, 0		@ ctrl register
110 	@ --- aligned to a cache line
127  * addr: cache-unaligned virtual address
150 	str	lr, [sp, #-4]!
151 	bl	v4wb_flush_kern_cache_all	@ clears IP
152 	mcr	p15, 0, ip, c9, c0, 0		@ invalidate RB
154 	mcr	p15, 0, ip, c8, c7, 0		@ invalidate I & D TLBs
181 	stmfd	sp!, {r4 - r6, lr}
185 	stmia	r0, {r4 - r6}			@ store cp regs
186 	ldmfd	sp!, {r4 - r6, pc}
190 	ldmia	r0, {r4 - r6}			@ load cp regs
191 	mov	ip, #0
192 	mcr	p15, 0, ip, c8, c7, 0		@ flush I+D TLBs
193 	mcr	p15, 0, ip, c7, c7, 0		@ flush I&D cache
194 	mcr	p15, 0, ip, c9, c0, 0		@ invalidate RB
195 	mcr	p15, 0, ip, c9, c0, 5		@ allow user space to use RB
219 	.size	__sa1100_setup, . - __sa1100_setup
237 	@ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
244 	string	cpu_sa1100_name, "StrongARM-1100"
245 	string	cpu_sa1110_name, "StrongARM-1110"
273 	.size	__\name\()_proc_info, . - __\name\()_proc_info