Lines Matching +full:4 +full:c0
38 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
41 mcr p15, 0, r0, c1, c0, 0 @ disable caches
56 .align 4
62 mcr p15, 0, ip, c7, c10, 4 @ drain WB
66 mrc p15, 0, ip, c1, c0, 0 @ ctrl register
70 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
80 .align 4
90 mcr p15, 0, r0, c7, c10, 4 @ drain WB
103 .align 4
114 mcr p15, 0, ip, c7, c10, 4 @ data write barrier
115 mcr p15, 0, ip, c7, c5, 4 @ prefetch flush
116 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
127 .align 4
134 mcr p15, 0, r0, c7, c10, 4 @ drain WB
144 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
155 mcr p15, 0, r0, c7, c10, 4 @ data write barrier
156 mcr p15, 0, r0, c7, c5, 4 @ prefetch flush
159 mcr p15, 0, r0, c3, c0 @ load domain access register
161 mrc p15, 0, r0, c1, c0 @ get control register v4