arm/mm/proc-arm946.S

25 #define CACHE_DSEGMENTS	4			/* fixed */
27 #define CACHE_DLIMIT	(CACHE_DSIZE * 4)	/* benchmark needed */
48 	mrc	p15, 0, r0, c1, c0, 0		@ ctrl register
51 	mcr	p15, 0, r0, c1, c0, 0		@ disable caches
65 	mcr	p15, 0, ip, c7, c10, 4		@ drain WB
66 	mrc	p15, 0, ip, c1, c0, 0		@ ctrl register
69 	mcr	p15, 0, ip, c1, c0, 0		@ ctrl register
79 	mcr	p15, 0, r0, c7, c0, 4		@ Wait for interrupt
111 	mov	r1, #(CACHE_DSEGMENTS - 1) << 29 @ 4 segments
112 1:	orr	r3, r1, #(CACHE_DENTRIES - 1) << 4 @ n entries
114 	subs	r3, r3, #1 << 4
121 	mcrne	p15, 0, ip, c7, c10, 4		@ drain WB
161 	mcrne	p15, 0, ip, c7, c10, 4		@ drain WB
199 	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
222 	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
250 	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
271 	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
295 	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
330 	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
339 	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
347 	mov	r0, #0x0000003F			@ base = 0, size = 4GB
348 	mcr	p15, 0, r0, c6,	c0, 0		@ set region 0, default
351 	ldr	r7, =CONFIG_DRAM_SIZE		@ size of RAM (must be >= 4KB)
356 	ldr	r7, =CONFIG_FLASH_SIZE		@ size of FLASH (must be >= 4KB)
361 	mcr	p15, 0, r0, c2, c0, 0		@ region 1,2 d-cacheable
362 	mcr	p15, 0, r0, c2, c0, 1		@ region 1,2 i-cacheable
368 	mcr	p15, 0, r0, c3, c0, 0
381 	mcr	p15, 0, r0, c5, c0, 2		@ set data access permission
382 	mcr	p15, 0, r0, c5, c0, 3		@ set inst. access permission
384 	mrc	p15, 0, r0, c1, c0		@ get control register