Lines Matching +full:4 +full:c0
17 /* ARM940T has a 4KB DCache comprising 256 lines of 4 words */
19 #define CACHE_DSEGMENTS 4
41 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
44 mcr p15, 0, r0, c1, c0, 0 @ disable caches
58 mcr p15, 0, ip, c7, c10, 4 @ drain WB
59 mrc p15, 0, ip, c1, c0, 0 @ ctrl register
62 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
72 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
117 mov r1, #(CACHE_DSEGMENTS - 1) << 4 @ 4 segments
122 subs r1, r1, #1 << 4
127 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
172 mov r1, #(CACHE_DSEGMENTS - 1) << 4 @ 4 segments
177 subs r1, r1, #1 << 4
180 mcr p15, 0, r0, c7, c10, 4 @ drain WB
195 mov r1, #(CACHE_DSEGMENTS - 1) << 4 @ 4 segments
200 subs r1, r1, #1 << 4
202 mcr p15, 0, ip, c7, c10, 4 @ drain WB
218 mov r1, #(CACHE_DSEGMENTS - 1) << 4 @ 4 segments
223 subs r1, r1, #1 << 4
226 mcr p15, 0, ip, c7, c10, 4 @ drain WB
241 mov r1, #(CACHE_DSEGMENTS - 1) << 4 @ 4 segments
251 subs r1, r1, #1 << 4
253 mcr p15, 0, ip, c7, c10, 4 @ drain WB
286 mcr p15, 0, r0, c7, c10, 4 @ drain WB
300 mov r0, #0x0000003F @ base = 0, size = 4GB
301 mcr p15, 0, r0, c6, c0, 0 @ set area 0, default
302 mcr p15, 0, r0, c6, c0, 1
305 ldr r7, =CONFIG_DRAM_SIZE >> 12 @ size of RAM (must be >= 4KB)
311 ldr r7, =CONFIG_FLASH_SIZE @ size of FLASH (must be >= 4KB)
317 mcr p15, 0, r0, c2, c0, 0 @ Region 1&2 cacheable
318 mcr p15, 0, r0, c2, c0, 1
324 mcr p15, 0, r0, c3, c0, 0
328 mcr p15, 0, r0, c5, c0, 0 @ all read/write access
329 mcr p15, 0, r0, c5, c0, 1
331 mrc p15, 0, r0, c1, c0 @ get control register