arm/mm/cache-v7.S

44 	mcr	p15, 2, r0, c0, c0, 0	@ select L1 data cache in CSSELR
46 	mrc	p15, 1, r0, c0, c0, 0	@ read cache geometry from CCSIDR
57 	add	r2, r2, #4		@ SetShift
69 	mrc	p15, 1, r0, c0, c0, 0	@ re-read cache geometry from CCSIDR
101 	mrc	p15, 1, r0, c0, c0, 1		@ read clidr, r0 = clidr
107 ALT_SMP(mrc	p15, 0, r2, c0, c0, 0)		@ read main ID register
109 	movw	r1, #:lower16:(0x410fc090 >> 4)	@ ID of ARM Cortex A9 r0p?
110 	movt	r1, #:upper16:(0x410fc090 >> 4)
111 	teq	r1, r2, lsr #4			@ test for errata affected core and if so...
129 	mrc	p15, 1, r0, c0, c0, 1		@ read clidr
144 	mcr	p15, 2, r10, c0, c0, 0		@ select current cache level in cssr
146 	mrc	p15, 1, r1, c0, c0, 0		@ read the new csidr
151 	add	r2, r2, #4			@ add 4 (line length offset)
180 	mcr	p15, 2, r10, c0, c0, 0		@ select current cache level in cssr