arm/kernel/head.S

107 	mrc	p15, 0, r9, c0, c0		@ get processor id
114 	mrc	p15, 0, r3, c0, c1, 4		@ read ID_MMFR0
196 1:	str	r3, [r0], #4
197 	str	r3, [r0], #4
198 	str	r3, [r0], #4
199 	str	r3, [r0], #4
211 	mov	r6, #4				@ PTRS_PER_PGD
215 	str	r7, [r0], #4			@ set top PGD entry bits
216 	str	r3, [r0], #4			@ set bottom PGD entry bits
218 	str	r3, [r0], #4			@ set bottom PGD entry bits
219 	str	r7, [r0], #4			@ set top PGD entry bits
227 	add	r4, r4, #4			@ we only write the bottom word
260 	str	r8, [r5, #4]			@ Save physical start of kernel (BE)
275 	str	r3, [r5, #4]			@ Save physical end of kernel (BE)
312 	sub	r4, r4, #4			@ Fixup page table pointer
335 	str	r7, [r0], #4
336 	str	r3, [r0], #4
338 	str	r3, [r0], #4
339 	str	r7, [r0], #4
343 	str	r3, [r0], #4
404 	mrc	p15, 0, r9, c0, c0		@ get processor id
438 	mrc	p15, 0, ip, c2, c0, 1	@ read TTBR1
439 	mcr	p15, 0, ip, c2, c0, 0	@ set TTBR0
444 	ldr	r0, [r7, #4]			@ get secondary_data.task
486 	mcr	p15, 0, r5, c3, c0, 0		@ load domain access register
487 	mcr	p15, 0, r4, c2, c0, 0		@ load page table pointer
511 	mcr	p15, 0, r0, c1, c0, 0		@ write control reg
512 	mrc	p15, 0, r3, c0, c0, 0		@ read id reg
537 	mrc	p15, 0, r0, c0, c0, 5	@ read MPIDR
553 	mrc	p15, 4, r0, c15, c0	@ get SCU base address
556 	ldr	r0, [r0, #4]		@ read SCU Config